From 2b1f45cad96de6dd346b5865bf7a92943429f598 Mon Sep 17 00:00:00 2001 From: Jonathan Balkind Date: Fri, 14 Mar 2025 14:39:36 -0700 Subject: [PATCH 1/3] Update CODEOWNERS with jbalkind and cfuguet (#2829) Updating @Jbalkind and adding @cfuguet to CODEOWNERS --- CODEOWNERS | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/CODEOWNERS b/CODEOWNERS index 9a4976dad..77038a3c8 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -7,9 +7,18 @@ core/mmu_sv39 @sjthales core/cvxif_example @Gchauvon core/cvxif_fu.sv @Gchauvon -# APU +# HPDCache + +core/cache_subsystem/hpdcache @cfuguet +core/cache_subsystem/cva6_hpdcache* @cfuguet +core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @cfuguet +core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @cfuguet + +# OpenPiton corev_apu/openpiton @Jbalkind +core/cache_subsystem/wt_l15_adapter.sv @Jbalkind +core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @Jbalkind ## Documentation From 0e2e5128b240ff069adddff8d20a322df985633e Mon Sep 17 00:00:00 2001 From: Katharina Date: Fri, 14 Mar 2025 22:42:29 +0100 Subject: [PATCH 2/3] Assign a default value to tinst in decoder (#2830) This PR assigns 0 to tinst by default. Even though tinst is only used when CVA6Cfg.RVH is enabled, I chose to assign it a default value in all configurations, since the signal is defined for all configurations. Fixes #2803 Co-authored-by: JeanRochCoulon --- core/decoder.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/core/decoder.sv b/core/decoder.sv index de52e7f23..98fc3b1c4 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -186,6 +186,7 @@ module decoder ecall = 1'b0; ebreak = 1'b0; check_fprm = 1'b0; + tinst = 32'h0; if (~ex_i.valid) begin case (instr.rtype.opcode) From b38c259c8cc948125f2080fcae903652c8202f49 Mon Sep 17 00:00:00 2001 From: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com> Date: Mon, 17 Mar 2025 17:35:43 +0100 Subject: [PATCH 3/3] Initialize compressed related signals in id_stage when RVC is disabled (#2833) Add else case to initialize signals going into decoder. Should fix #2819 --- core/id_stage.sv | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/core/id_stage.sv b/core/id_stage.sv index d37554db4..121b4388b 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -269,6 +269,13 @@ module id_stage #( end else begin assign stall_instr_fetch[0] = stall_macro_deco; end + end else begin + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign is_illegal_rvc[i] = 1'b0; + assign instruction_rvc[i] = fetch_entry_i[i].instruction; + assign is_compressed_rvc[i] = 1'b0; + assign stall_instr_fetch[i] = 1'b0; + end end // ---------------------------------------------------------