From 5b274352e1e6ec74acf925b4b8a6cdc92557c428 Mon Sep 17 00:00:00 2001
From: Tanuj Khandelwal <tanuj-kumar.khandelwal@cea.fr>
Date: Wed, 12 Mar 2025 09:40:46 +0100
Subject: [PATCH] added correct reset val

---
 config/riscv-config/cv64a60ax/spec/isa_spec.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/config/riscv-config/cv64a60ax/spec/isa_spec.yaml b/config/riscv-config/cv64a60ax/spec/isa_spec.yaml
index 3ae10eed6..cef6c746b 100644
--- a/config/riscv-config/cv64a60ax/spec/isa_spec.yaml
+++ b/config/riscv-config/cv64a60ax/spec/isa_spec.yaml
@@ -23,7 +23,7 @@ hart0: &hart0
   physical_addr_sz: 39
   pmp_granularity: 10 # FIXME: To verify
   misa:
-    # reset-val: 0xC00000000214312F # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25
+   reset-val: 0x800000000014312D # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25
    rv64:
      accessible: true
      mxl: