From 615b8176419941802bdd78b651479cab16140ebf Mon Sep 17 00:00:00 2001
From: Florian Zaruba <fl.zaruba@be4web.net>
Date: Thu, 10 Aug 2017 15:49:44 +0200
Subject: [PATCH] :bug: Fix debug rvalid and also halt if not fetchen

---
 src/ariane.sv     |  1 +
 src/debug_unit.sv | 13 +++++++------
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/ariane.sv b/src/ariane.sv
index 9ea535a9a..34f5b490a 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -574,6 +574,7 @@ module ariane
         .commit_ack_i      ( commit_ack                ),
         .ex_i              ( ex_commit                 ),
         .halt_o            ( halt_debug_ctrl           ),
+        .fetch_enable_i    ( fetch_enable              ),
 
         .debug_pc_o        ( pc_debug_pcgen            ),
         .debug_set_pc_o    ( set_pc_debug              ),
diff --git a/src/debug_unit.sv b/src/debug_unit.sv
index 270f6f776..f1540474d 100755
--- a/src/debug_unit.sv
+++ b/src/debug_unit.sv
@@ -27,6 +27,7 @@ module debug_unit (
     input  logic                commit_ack_i,
     input  exception            ex_i,           // instruction caused an exception
     output logic                halt_o,         // halt the hart
+    input  logic                fetch_enable_i, // fetch enable signal
     // GPR interface
     output logic                debug_gpr_req_o,
     output logic [4:0]          debug_gpr_addr_o,
@@ -98,7 +99,7 @@ module debug_unit (
     always_comb begin : debug_ctrl
         debug_gnt_o     = 1'b0;
         rdata_n         = 'b0;
-        rvalid_n        = 1'b0;
+        rvalid_n        = debug_req_i;
 
         halt_req        = 1'b0;
         resume_req      = 1'b0;
@@ -269,7 +270,7 @@ module debug_unit (
             HALT_REQ: begin
                 halt_o = 1'b1;
                 // we've got a valid instruction in the commit stage so we can proceed to the halted state
-                if (commit_instr_i.valid) begin
+                if (commit_instr_i.valid || !fetch_enable_i) begin
                     NS = HALTED;
                 end
             end
@@ -335,10 +336,10 @@ module debug_unit (
     // check that no registers are accessed when we are not in debug mode
     assert property (
       @(posedge clk_i) (debug_req_i) |-> ((debug_halted_o == 1'b1) ||
-                                        ((debug_addr_i[14] != 1'b1) &&
-                                         (debug_addr_i[13:7] != 5'b0_1001)  &&
-                                         (debug_addr_i[13:7] != 5'b0_1000)) ) )
-      else $warning("Trying to access internal debug registers while core is not stalled");
+                                         ((debug_addr_i[14] != 1'b1) &&
+                                          (debug_addr_i[13:7] != 5'b0_1001)  &&
+                                          (debug_addr_i[13:7] != 5'b0_1000)) ) )
+      else $warning("Trying to access internal debug registers while core is not halted");
 
     // check that all accesses are word-aligned
     assert property (