diff --git a/Makefile b/Makefile index 6a392d3c1..d030bf0a5 100644 --- a/Makefile +++ b/Makefile @@ -72,6 +72,7 @@ $(tests): vsim${questa_version} +UVM_TESTNAME=$@_test +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $@_tb_optimized build-moore: + [ ! -e .moore ] || rm .moore # $(moore) compile src/fifo.sv $(foreach src_file, $(src), $(moore) compile $(src_file);) diff --git a/include/ariane_pkg.svh b/include/ariane_pkg.svh index 91cd8a384..5d55fcb06 100644 --- a/include/ariane_pkg.svh +++ b/include/ariane_pkg.svh @@ -68,7 +68,7 @@ package ariane_pkg; // CSR functions MRET, SRET, URET, ECALL, CSR_WRITE, CSR_READ, CSR_SET, CSR_CLEAR, // LSU functions - LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU, SBU + LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU } fu_op; // --------------- diff --git a/src/commit_stage.sv b/src/commit_stage.sv index 529f5e62a..2a0e48136 100644 --- a/src/commit_stage.sv +++ b/src/commit_stage.sv @@ -23,7 +23,7 @@ module commit_stage ( input logic rst_ni, // Asynchronous reset active low output priv_lvl_t priv_lvl_o, // privilege level out - output exception exception_o, // take exception to controller and if + output exception exception_o, // take exception to controller // from scoreboard input scoreboard_entry commit_instr_i, @@ -36,7 +36,7 @@ module commit_stage ( // to/from CSR file output logic [63:0] pc_o, - input fu_op csr_op_o, + output fu_op csr_op_o, output logic [63:0] csr_wdata_o, output logic [63:0] csr_rdata_i, input exception csr_exception_i, @@ -48,24 +48,61 @@ module commit_stage ( ); assign waddr_a_o = commit_instr_i.rd; - assign wdata_a_o = commit_instr_i.result; assign pc_o = commit_instr_i.pc; - // commit instruction - // write register file + logic exception; + + // ------------------- + // Commit Instruction + // ------------------- + // write register file or commit instruction in LSU or CSR Buffer always_comb begin : commit // default assignments commit_ack_o = 1'b0; we_a_o = 1'b0; - if (commit_instr_i.valid) begin - we_a_o = 1'b1; - commit_ack_o = 1'b1; + commit_lsu_o = 1'b0; + commit_csr_o = 1'b0; + exception = 1'b0; + wdata_a_o = commit_instr_i.result; + csr_op_o = ADD; // this corresponds to a CSR NOP + // we will not commit the instruction if we took an exception + if (~(commit_instr_i.ex.valid || csr_exception_i.valid)) begin + if (commit_instr_i.valid) begin + // we can definitely write the register file + // if the instruction is not committing anything the destination + // register will be the all zero register. + we_a_o = 1'b1; + commit_ack_o = 1'b1; + // check whether the instruction we retire was a store + if (commit_instr_i.op inside {SD, SW, SH, SB}) begin + commit_lsu_o = 1'b1; + end + // --------- + // CSR Logic + // --------- + // check whether the instruction we retire was a CSR instruction + if (commit_instr_i.fu == CSR) begin + // write the CSR file + commit_csr_o = 1'b1; + wdata_a_o = csr_rdata_i; + csr_op_o = commit_instr_i.op; + csr_wdata_o = commit_instr_i.result; + end + end + end else begin // we got an exception either from the instruction directly or from the CS regfile + exception = 1'b1; end end - // CSR logic - // privilege check - // exception logic + // ---------------- + // Exception Logic + // ---------------- + // here we know for sure that we are taking the exception + always_comb begin : exception_handling + if (exception) begin + + end + end endmodule \ No newline at end of file diff --git a/src/issue_read_operands.sv b/src/issue_read_operands.sv index 5bfdbf1c1..91d728220 100644 --- a/src/issue_read_operands.sv +++ b/src/issue_read_operands.sv @@ -193,11 +193,7 @@ module issue_read_operands ( operand_a_n = {52'b0, issue_instr_i.rs1}; end // or is it an immediate (including PC), this is not the case for a store - if (issue_instr_i.use_imm && issue_instr_i.op != SD - && issue_instr_i.op != SW - && issue_instr_i.op != SH - && issue_instr_i.op != SB - && issue_instr_i.op != SBU ) begin + if (issue_instr_i.use_imm && (issue_instr_i.op inside {SD, SW, SH, SB})) begin operand_b_n = issue_instr_i.result; end // immediates are the third operands in the store case diff --git a/src/lsu.sv b/src/lsu.sv index e98d96629..0a4b2e5f3 100644 --- a/src/lsu.sv +++ b/src/lsu.sv @@ -397,7 +397,7 @@ module lsu #( // all loads go here LD, LW, LWU, LH, LHU, LB, LBU: op = LD_OP; // all stores go here - SD, SW, SH, SB, SBU: op = ST_OP; + SD, SW, SH, SB: op = ST_OP; // not relevant for the lsu default: op = NONE; endcase diff --git a/tb/agents/lsu_if/lsu_if_driver.svh b/tb/agents/lsu_if/lsu_if_driver.svh index a6492930d..b1f92d10e 100644 --- a/tb/agents/lsu_if/lsu_if_driver.svh +++ b/tb/agents/lsu_if/lsu_if_driver.svh @@ -61,7 +61,7 @@ class lsu_if_driver extends uvm_driver #(lsu_if_seq_item); @(m_vif.mck); // spawn a commit thread that will eventually commit this instruction case (cmd.operator) - SD, SW, SH, SB, SBU: + SD, SW, SH, SB: fork commit_thread: begin lock.get(1); diff --git a/tb/agents/lsu_if/lsu_if_seq_item.svh b/tb/agents/lsu_if/lsu_if_seq_item.svh index 7680a7a81..097c0d77b 100644 --- a/tb/agents/lsu_if/lsu_if_seq_item.svh +++ b/tb/agents/lsu_if/lsu_if_seq_item.svh @@ -30,7 +30,7 @@ class lsu_if_seq_item extends uvm_sequence_item; rand int requestDelay; logic [63:0] result; - const fu_op allowed_ops[] = {LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU, SBU}; + const fu_op allowed_ops[] = {LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU}; // constraint the delay we allow constraint delay_bounds { requestDelay inside {[0:10]};