diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py
index 92e192bd2..f84f46942 100644
--- a/.gitlab-ci/scripts/report_benchmark.py
+++ b/.gitlab-ci/scripts/report_benchmark.py
@@ -17,8 +17,8 @@ iterations = None
 # Keep it up-to-date with compiler version and core performance improvements
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
-    'dhrystone': 221425,
-    'coremark': 697868,
+    'dhrystone': 217900,
+    'coremark': 670777,
 }
 
 for arg in sys.argv[1:]:
diff --git a/cva6/regress/dv-generated-tests.sh b/cva6/regress/dv-generated-tests.sh
index f2f6492d9..135eb845a 100644
--- a/cva6/regress/dv-generated-tests.sh
+++ b/cva6/regress/dv-generated-tests.sh
@@ -104,7 +104,7 @@ printf "+=======================================================================
 j=0
 while [[ $j -lt ${#TEST_NAME[@]} ]];do
   cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
-  python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
+  python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 --isa_extension=zicsr,zifencei
   n=0
   echo "Generate the test : ${TEST_NAME[j]}"
 #this while loop detects the failed tests from the log file and remove them
@@ -128,6 +128,6 @@ j=0
 elif [[ "$list_num" = 0 ]];then
    printf "==== Execute Directed tests to improve functional coverage of isa, by hiting some corners !!! ====\n\n"
    printf "==== These tests are generated by RISCV-DV before modify to hit some specific values ====\n\n"
-   python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike
+   python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike --isa_extension=zicsr,zifencei
 fi
 cd -
diff --git a/cva6/regress/dv-riscv-compliance.sh b/cva6/regress/dv-riscv-compliance.sh
index 452713fcd..ba779fa49 100755
--- a/cva6/regress/dv-riscv-compliance.sh
+++ b/cva6/regress/dv-riscv-compliance.sh
@@ -27,5 +27,5 @@ if ! [ -n "$DV_SIMULATORS" ]; then
 fi
 
 cd cva6/sim
-python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
+python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --isa_extension=zicsr,zifencei
 cd -
diff --git a/cva6/regress/dv-riscv-tests.sh b/cva6/regress/dv-riscv-tests.sh
index bba9f392a..4ac10cd03 100755
--- a/cva6/regress/dv-riscv-tests.sh
+++ b/cva6/regress/dv-riscv-tests.sh
@@ -34,6 +34,6 @@ fi
 cd cva6/sim
 for TESTLIST in $DV_TESTLISTS
 do
-  python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS
+  python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS --isa_extension=zicsr,zifencei
 done
 cd -
diff --git a/cva6/regress/smoke-tests.sh b/cva6/regress/smoke-tests.sh
index d1016a054..e0a4c827c 100644
--- a/cva6/regress/smoke-tests.sh
+++ b/cva6/regress/smoke-tests.sh
@@ -20,6 +20,7 @@ source ./cva6/regress/install-riscv-compliance.sh
 source ./cva6/regress/install-riscv-tests.sh
 source ./cva6/regress/install-riscv-arch-test.sh
 
+
 if ! [ -n "$DV_SIMULATORS" ]; then
   DV_SIMULATORS=vcs-testharness,spike
 fi
@@ -37,8 +38,8 @@ make clean_all
 python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
 python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
 python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS  --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
-python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\
-  --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld"
+python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\
+  --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common"
 make -C ../../core-v-cores/cva6 clean
 make clean_all
 
diff --git a/cva6/sim/cva6.py b/cva6/sim/cva6.py
index 7799fae01..58f31ef5f 100644
--- a/cva6/sim/cva6.py
+++ b/cva6/sim/cva6.py
@@ -100,7 +100,7 @@ def parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd):
   for entry in yaml_data:
     if entry['iss'] == iss:
       logging.info("Found matching ISS: %s" % entry['iss'])
-      m = re.search(r"rv(?P<xlen>[0-9]+?)(?P<variant>[a-z]+?)$", isa)
+      m = re.search(r"rv(?P<xlen>[0-9]+?)(?P<variant>[a-z]+(_[szx]\w+)*)$", isa)
       if m: logging.info("ISA %0s" % isa)
       else: logging.error("Illegal ISA %0s" % isa)
 
@@ -349,7 +349,9 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd, linker):
       asm = prefix + ".S"
       elf = prefix + ".o"
       binary = prefix + ".bin"
-      test_isa = isa
+      test_isa=re.match("[a-z0-9A-Z]+", isa)
+      test_isa=test_isa.group()
+      isa_ext=isa
       if not os.path.isfile(asm) and not debug_cmd:
         logging.error("Cannot find assembly test: %s\n", asm)
         sys.exit(RET_FAIL)
@@ -366,10 +368,15 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd, linker):
         # Disable compressed instruction
         if re.search('disable_compressed_instr=1', test['gen_opts']):
           test_isa = re.sub("c",  "", test_isa)
+          #add z,s,x extensions to the isa if there are some
+          if isa_extension_list !=['none']:
+            for i in isa_extension_list:
+              test_isa += (f"_{i}")
+          isa_ext=test_isa
       # If march/mabi is not defined in the test gcc_opts, use the default
       # setting from the command line.
       if not re.search('march', cmd):
-        cmd += (" -march=%s" % test_isa)
+        cmd += (" -march=%s" % isa_ext)
       if not re.search('mabi', cmd):
         cmd += (" -mabi=%s" % mabi)
       logging.info("Compiling %s" % asm)
@@ -542,7 +549,7 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
   report = ("%s/iss_regr.log" % output_dir).rstrip()
   c = re.sub(r"^.*\/", "", c_test)
   c = re.sub(r"\.c$", "", c)
-  prefix = ("%s/directed_c_tests/%s"  % (output_dir, c))
+  prefix = (f"{output_dir}/directed_c_tests/{c}")
   elf = prefix + ".o"
   binary = prefix + ".bin"
   iss_list = iss_opts.split(",")
@@ -553,9 +560,9 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
   cmd = ("%s -mcmodel=medany -nostdlib \
          -nostartfiles %s \
          -I%s/dv/user_extension \
-         -T%s %s -o %s " % \
-         (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd,
-                      linker, gcc_opts, elf))
+          -T%s %s -o %s " % \
+         (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd, 
+					  linker, gcc_opts, elf))
   cmd += (" -march=%s" % isa)
   cmd += (" -mabi=%s" % mabi)
   run_cmd(cmd, debug_cmd = debug_cmd)
@@ -829,6 +836,8 @@ def setup_parser():
                       help="Run test N times with random seed")
   parser.add_argument("--sv_seed", type=str, default="1",
                       help="Run test with a specific seed")
+  parser.add_argument("--isa_extension", type=str, default="zicsr",
+                      help="Choose additional z, s, x extensions")
   return parser
 
 
@@ -840,6 +849,11 @@ def load_config(args, cwd):
   Returns:
       Loaded configuration dictionary.
   """
+  
+  global isa_extension_list
+  isa_extension_list = args.isa_extension.split(",")  
+  
+  
   if args.debug:
     args.debug = open(args.debug, "w")
   if not args.csr_yaml:
@@ -975,6 +989,13 @@ def main():
     os.environ["CVA6_DV_ROOT"]  = cwd + "/../env/corev-dv"
     setup_logging(args.verbose)
     logg = logging.getLogger()
+    #print environment softwares
+    gcc_version=get_env_var("RISCV_GCC")
+    logging.info("GCC Version : %s" % (gcc_version))
+    spike_version=get_env_var("SPIKE_ROOT")
+    logging.info("Spike Version : %s" % (spike_version))
+    verilator_version=run_cmd("verilator --version")
+    logging.info("Verilator Version : %s" % (verilator_version))
     # create file handler which logs even debug messages
     fh = logging.FileHandler('logfile.log')
     fh.setLevel(logging.DEBUG)
@@ -987,7 +1008,12 @@ def main():
     cfg = load_config(args, cwd)
     # Create output directory
     output_dir = create_output(args.o, args.noclean, cwd+"/out_")
-
+    
+    #add z,s,x extensions to the isa if there are some
+    if isa_extension_list !=['none']:
+      for i in isa_extension_list:
+        args.isa += (f"_{i}")
+        
     if args.verilog_style_check:
       logging.debug("Run style check")
       style_err = run_cmd("verilog_style/run.sh")