diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv index e09d701fb..720cb4800 100644 --- a/include/ariane_pkg.sv +++ b/include/ariane_pkg.sv @@ -18,7 +18,7 @@ package ariane_pkg; localparam NR_SB_ENTRIES = 8; // number of scoreboard entries localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits // to uniquely identify the entry in the scoreboard - localparam NR_WB_PORTS = 4; + localparam NR_WB_PORTS = 5; localparam ASID_WIDTH = 1; localparam BTB_ENTRIES = 8; localparam BITS_SATURATION_COUNTER = 2; @@ -97,7 +97,7 @@ package ariane_pkg; // Multiplications MUL, MULH, MULHU, MULHSU, MULW, // Divisions - DIV, DIVU, REM, REMU, DIV, DIVU, DIVW, DIVWU, REM, REMU, REMW, REMWU + DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW } fu_op; typedef struct packed { diff --git a/src/ariane.sv b/src/ariane.sv index 66c605cc6..76029f22f 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -170,6 +170,9 @@ module ariane // MULT logic mult_ready_ex_id; logic mult_valid_id_ex; + logic [TRANS_ID_BITS-1:0] mult_trans_id_ex_id; + logic [63:0] mult_result_ex_id; + logic mult_valid_ex_id; // CSR logic csr_ready_ex_id; logic csr_valid_id_ex; @@ -376,10 +379,10 @@ module ariane .csr_ready_i ( csr_ready_ex_id ), .csr_valid_o ( csr_valid_id_ex ), - .trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id, branch_trans_id_ex_id, csr_trans_id_ex_id }), - .wdata_i ( {alu_result_ex_id, lsu_result_ex_id, branch_result_ex_id, csr_result_ex_id }), - .ex_ex_i ( {{$bits(exception){1'b0}}, lsu_exception_ex_id, branch_exception_ex_id, {$bits(exception){1'b0}} }), - .wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, branch_valid_ex_id, csr_valid_ex_id }), + .trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id, branch_trans_id_ex_id, csr_trans_id_ex_id, mult_trans_id_ex_id }), + .wdata_i ( {alu_result_ex_id, lsu_result_ex_id, branch_result_ex_id, csr_result_ex_id, mult_result_ex_id }), + .ex_ex_i ( {{$bits(exception){1'b0}}, lsu_exception_ex_id, branch_exception_ex_id, {$bits(exception){1'b0}}, {$bits(exception){1'b0}} }), + .wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, branch_valid_ex_id, csr_valid_ex_id, mult_valid_ex_id }), .waddr_a_i ( waddr_a_commit_id ), .wdata_a_i ( wdata_a_commit_id ), @@ -457,6 +460,9 @@ module ariane .mult_ready_o ( mult_ready_ex_id ), .mult_valid_i ( mult_valid_id_ex ), + .mult_trans_id_o ( mult_trans_id_ex_id ), + .mult_result_o ( mult_result_ex_id ), + .mult_valid_o ( mult_valid_ex_id ), .* ); diff --git a/src/decoder.sv b/src/decoder.sv index af3bb4140..cb936c395 100644 --- a/src/decoder.sv +++ b/src/decoder.sv @@ -273,6 +273,7 @@ module decoder ( // Multiplications {7'b000_0001, 3'b000}: instruction_o.op = MULW; {7'b000_0001, 3'b100}: instruction_o.op = DIVW; + {7'b000_0001, 3'b101}: instruction_o.op = DIVUW; {7'b000_0001, 3'b110}: instruction_o.op = REMW; {7'b000_0001, 3'b111}: instruction_o.op = REMUW; diff --git a/src/div.sv b/src/div.sv index 950f5a283..ecc42fec0 100644 --- a/src/div.sv +++ b/src/div.sv @@ -20,7 +20,7 @@ // module div ( input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic rst_ni // Asynchronous reset active low ); diff --git a/src/ex_stage.sv b/src/ex_stage.sv index 7be2db181..2e0321b5c 100644 --- a/src/ex_stage.sv +++ b/src/ex_stage.sv @@ -62,7 +62,6 @@ module ex_stage #( input logic lsu_commit_i, output exception lsu_exception_o, output logic no_st_pending_o, - // CSR output logic csr_ready_o, input logic csr_valid_i, @@ -71,7 +70,14 @@ module ex_stage #( output logic csr_valid_o, output logic [11:0] csr_addr_o, input logic csr_commit_i, - // memory management + // MULT + output logic mult_ready_o, // FU is ready + input logic mult_valid_i, // Output is valid + output logic [TRANS_ID_BITS-1:0] mult_trans_id_o, + output logic [63:0] mult_result_o, + output logic mult_valid_o, + + // Memory Management input logic enable_translation_i, input logic en_ld_st_translation_i, input logic flush_tlb_i, @@ -105,11 +111,7 @@ module ex_stage #( output logic data_if_tag_valid_o, input logic data_if_data_gnt_i, input logic data_if_data_rvalid_i, - input logic [63:0] data_if_data_rdata_i, - - // MULT - output logic mult_ready_o, // FU is ready - input logic mult_valid_i // Output is valid + input logic [63:0] data_if_data_rdata_i ); // ----- @@ -151,4 +153,4 @@ module ex_stage #( ); -endmodule \ No newline at end of file +endmodule diff --git a/src/mult.sv b/src/mult.sv index 6364dbe82..9db8d73af 100644 --- a/src/mult.sv +++ b/src/mult.sv @@ -31,7 +31,6 @@ module mult input logic [63:0] operand_a_i, input logic [63:0] operand_b_i, output logic [63:0] result_o, - output logic [63:0] result_o, output logic mult_valid_o, output logic mult_ready_o, output logic [TRANS_ID_BITS-1:0] mult_trans_id_o