diff --git a/Makefile b/Makefile
index cbab5c45b..bb933ff4c 100644
--- a/Makefile
+++ b/Makefile
@@ -43,7 +43,7 @@ riscv-tests = rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-a
 				rv64mi-p-csr rv64mi-p-mcsr rv64mi-p-illegal \
 				rv64mi-p-ma_addr rv64mi-p-ma_fetch rv64mi-p-sbreak rv64mi-p-scall \
 				rv64si-p-csr rv64si-p-ma_fetch rv64si-p-scall rv64si-p-wfi rv64si-p-sbreak \
-				rv64si-p-dirty
+				rv64si-p-dirty rv64uc-p-rvc
 
 
 riscv-test = rv64ui-p-add
diff --git a/src/pcgen.sv b/src/pcgen.sv
index cec197c07..63d67cc4b 100644
--- a/src/pcgen.sv
+++ b/src/pcgen.sv
@@ -91,7 +91,9 @@ module pcgen (
         // 1. Predict taken
         // -------------------------------
         // only predict if the IF stage is ready, otherwise we might take the predicted PC away which will end in a endless loop
-        if (if_ready_i && branch_predict_btb.valid && branch_predict_btb.predict_taken) begin
+        // also check if we fetched on a half word (npc_q[1] == 1), it might be the case that we need the next 16 byte of the following instruction
+        // prediction could potentially prevent us from getting them
+        if (if_ready_i && branch_predict_btb.valid && branch_predict_btb.predict_taken && !npc_q[1]) begin
             npc_n = branch_predict_btb.predict_address;
         end
         // -------------------------------