From 7046737969991c21c5d17b79c730a50c97873db5 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Thu, 16 Dec 2021 10:48:40 +0100 Subject: [PATCH] Flist.cv64a6_imafdc_sv39_gate: Flist dedicated to gate simulation (#778) Signed-off-by: Jean-Roch Coulon --- core/Flist.cv64a6_imafdc_sv39_gate | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 core/Flist.cv64a6_imafdc_sv39_gate diff --git a/core/Flist.cv64a6_imafdc_sv39_gate b/core/Flist.cv64a6_imafdc_sv39_gate new file mode 100644 index 000000000..d5f71a1db --- /dev/null +++ b/core/Flist.cv64a6_imafdc_sv39_gate @@ -0,0 +1,26 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com) +# + +${CVA6_REPO_DIR}/core/include/cv64a6_imafdc_sv39_config_pkg.sv +${CVA6_REPO_DIR}/core/include/riscv_pkg.sv +${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv +${CVA6_REPO_DIR}/core/include/ariane_pkg.sv +${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv +${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv + +${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv +${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv +${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv +${CVA6_REPO_DIR}/core/include/axi_intf.sv +${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv + +${CVA6_REPO_DIR}/${LIB_VERILOG} +${CVA6_REPO_DIR}/pd/synth/ariane_synth_modified.v +${CVA6_REPO_DIR}/pd/synth/SyncSpRamBeNx64_1.sv