diff --git a/src/util/instruction_trace_item.svh b/src/util/instruction_trace_item.svh
index 740b55bf8..dfd893c30 100755
--- a/src/util/instruction_trace_item.svh
+++ b/src/util/instruction_trace_item.svh
@@ -149,12 +149,14 @@ class instruction_trace_item;
             INSTR_SRA:                 s = this.printRInstr("sra");
             INSTR_OR:                  s = this.printRInstr("or");
             INSTR_AND:                 s = this.printRInstr("and");
+            INSTR_MUL:                 s = this.printMulInstr(1'b0);
             // OP32
             INSTR_ADDW:                s = this.printRInstr("addw");
             INSTR_SUBW:                s = this.printRInstr("subw");
             INSTR_SLLW:                s = this.printRInstr("sllw");
             INSTR_SRLW:                s = this.printRInstr("srlw");
             INSTR_SRAW:                s = this.printRInstr("sraw");
+            INSTR_MULW:                s = this.printMulInstr(1'b1);
             // FENCE
             INSTR_FENCE:               s = this.printMnemonic("fence");
             INSTR_FENCEI:              s = this.printMnemonic("fence.i");
@@ -354,47 +356,24 @@ class instruction_trace_item;
 
     endfunction // printSInstr
 
-    function string printMulInstr();
-      // string mnemonic;
-      // string str_suf;
-      // string str_imm;
-      // string str_asm;
-      // begin
+    function string printMulInstr(logic is_op32);
+        string s = "";
 
-      //   // always read rs1 and rs2 and write rd
-      //   regs_read.push_back('{rs1, rs1_value});
-      //   regs_read.push_back('{rs2, rs2_value});
-      //   regs_write.push_back('{rd, 'x});
+        case (this.instr[14:12])
+            3'b000: s = "mul";
+            3'b001: s = "mulh";
+            3'b010: s = "mulhsu";
+            3'b011: s = "mulhu";
+            3'b100: s = "div";
+            3'b101: s = "divu";
+            3'b110: s = "rem";
+            3'b111: s = "remu";
+        endcase
+        // if it is a 32 bit instruction concatenate a w on it
+        if (is_op32)
+            s = {s, "w"};
 
-      //   if (instr[12])
-      //     regs_read.push_back('{rd, rs3_value});
+        return this.printRInstr(s);
 
-      //   case ({instr[31:30], instr[14]})
-      //     3'b000: str_suf = "u";
-      //     3'b001: str_suf = "uR";
-      //     3'b010: str_suf = "hhu";
-      //     3'b011: str_suf = "hhuR";
-      //     3'b100: str_suf = "s";
-      //     3'b101: str_suf = "sR";
-      //     3'b110: str_suf = "hhs";
-      //     3'b111: str_suf = "hhsR";
-      //   endcase
-
-      //   if (instr[12])
-      //     mnemonic = "p.mac";
-      //   else
-      //     mnemonic = "p.mul";
-
-      //   if (imm_s3_type[4:0] != 5'b00000)
-      //     str_asm = $sformatf("%s%sN", mnemonic, str_suf);
-      //   else
-      //     str_asm = $sformatf("%s%s", mnemonic, str_suf);
-
-      //   if (instr[29:25] != 5'b00000)
-      //     str = $sformatf("%-16s x%0d, x%0d, x%0d, %0d", str_asm, rd, rs1, rs2, $unsigned(imm_s3_type[4:0]));
-      //   else
-      //     str = $sformatf("%-16s x%0d, x%0d, x%0d", str_asm, rd, rs1, rs2);
-      // end
-      return "";
     endfunction
   endclass
diff --git a/src/util/instruction_tracer_defines.svh b/src/util/instruction_tracer_defines.svh
index f26519e18..f955e358c 100755
--- a/src/util/instruction_tracer_defines.svh
+++ b/src/util/instruction_tracer_defines.svh
@@ -63,6 +63,7 @@ parameter INSTR_SRL      =  { 7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OP };
 parameter INSTR_SRA      =  { 7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OP };
 parameter INSTR_OR       =  { 7'b0000000, 10'b?, 3'b110, 5'b?, OPCODE_OP };
 parameter INSTR_AND      =  { 7'b0000000, 10'b?, 3'b111, 5'b?, OPCODE_OP };
+parameter INSTR_MUL      =  { 7'b0000001, 10'b?, 3'b???, 5'b?, OPCODE_OP };
 
 // OP32
 parameter INSTR_ADDW     =  { 7'b0000000, 10'b?, 3'b000, 5'b?, OPCODE_OP32 };
@@ -70,6 +71,7 @@ parameter INSTR_SUBW     =  { 7'b0100000, 10'b?, 3'b000, 5'b?, OPCODE_OP32 };
 parameter INSTR_SLLW     =  { 7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OP32 };
 parameter INSTR_SRLW     =  { 7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OP32 };
 parameter INSTR_SRAW     =  { 7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OP32 };
+parameter INSTR_MULW     =  { 7'b0000001, 10'b?, 3'b???, 5'b?, OPCODE_OP32 };
 
 // FENCE
 parameter INSTR_FENCE    =  { 4'b0, 8'b?, 13'b0, OPCODE_FENCE };
@@ -106,4 +108,4 @@ parameter INSTR_REMU     =  { 7'b0000001, 10'b?, 3'b111, 5'b?, OPCODE_OP };
 
 // Load/Stores
 parameter INSTR_LOAD     =  {25'b?, OPCODE_LOAD};
-parameter INSTR_STORE    =  {25'b?, OPCODE_STORE};
\ No newline at end of file
+parameter INSTR_STORE    =  {25'b?, OPCODE_STORE};