diff --git a/Bender.yml b/Bender.yml index ff8d8e021..a680dd801 100644 --- a/Bender.yml +++ b/Bender.yml @@ -81,10 +81,8 @@ sources: # - vendor/pulp-platform/axi/src/axi_pkg.sv # Packages - - core/include/ariane_axi_pkg.sv - core/include/wt_cache_pkg.sv - core/include/std_cache_pkg.sv - - core/include/axi_intf.sv - core/include/acc_pkg.sv # for all the below files use Flist.cva6 as baseline and also look at Makefile pd/synth diff --git a/Flist.ariane b/Flist.ariane index 236233b58..057610d12 100644 --- a/Flist.ariane +++ b/Flist.ariane @@ -21,13 +21,14 @@ core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv core/include/riscv_pkg.sv -corev_apu/riscv-dbg/src/dm_pkg.sv +core/include/ariane_dm_pkg.sv +common/local/rvfi/rvfi_pkg.sv core/include/ariane_pkg.sv corev_apu/tb/ariane_soc_pkg.sv vendor/pulp-platform/axi/src/axi_pkg.sv -core/include/ariane_axi_pkg.sv +corev_apu/tb/include/ariane_axi_pkg.sv core/include/wt_cache_pkg.sv -core/include/axi_intf.sv +corev_apu/tb/axi_intf.sv vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv core/include/cvxif_pkg.sv vendor/pulp-platform/common_cells/src/cf_math_pkg.sv @@ -55,7 +56,7 @@ vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv common/local/util/tc_sram_wrapper.sv vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv -core/axi_adapter.sv +core/cache_subsystem/axi_adapter.sv core/alu.sv core/fpu_wrap.sv corev_apu/src/ariane.sv @@ -106,6 +107,7 @@ core/cache_subsystem/wt_cache_subsystem.sv corev_apu/clint/clint.sv corev_apu/clint/axi_lite_interface.sv corev_apu/riscv-dbg/debug_rom/debug_rom.sv +corev_apu/riscv-dbg/src/dm_pkg.sv corev_apu/riscv-dbg/src/dm_csrs.sv corev_apu/riscv-dbg/src/dm_mem.sv corev_apu/riscv-dbg/src/dm_top.sv diff --git a/Makefile b/Makefile index 8fdd8c4cc..fc68de335 100644 --- a/Makefile +++ b/Makefile @@ -95,6 +95,8 @@ endif # Sources # Package files -> compile first ariane_pkg := \ + corev_apu/tb/ariane_axi_pkg.sv \ + corev_apu/tb/axi_intf.sv \ corev_apu/register_interface/src/reg_intf.sv \ corev_apu/tb/ariane_soc_pkg.sv \ corev_apu/riscv-dbg/src/dm_pkg.sv \ diff --git a/core/Flist.cva6 b/core/Flist.cva6 index 8ffb28ffd..a013ea705 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -60,14 +60,11 @@ ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv ${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv // Note: depends on fpnew_pkg, above ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv -// TODO: ariane_axi_pkg is dependent on this. ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv // Packages -${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv ${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv -${CVA6_REPO_DIR}/core/include/axi_intf.sv ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv ${CVA6_REPO_DIR}/core/include/acc_pkg.sv diff --git a/core/Flist.cva6_gate b/core/Flist.cva6_gate index 5819cc9c2..490fb04f6 100644 --- a/core/Flist.cva6_gate +++ b/core/Flist.cva6_gate @@ -12,15 +12,12 @@ ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv ${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv -// TODO: ariane_axi_pkg is dependent on this. ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv ${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv -${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv ${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv -${CVA6_REPO_DIR}/core/include/axi_intf.sv ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv ${LIB_VERILOG} diff --git a/core/axi_shim.sv b/core/axi_shim.sv index a495157b8..09e0213c2 100644 --- a/core/axi_shim.sv +++ b/core/axi_shim.sv @@ -21,13 +21,9 @@ module axi_shim #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, - parameter int unsigned AxiUserWidth = 64, // data width in dwords, this is also the maximum burst length, must be >=2 parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2 - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdWidth = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -35,35 +31,35 @@ module axi_shim #( // request input logic rd_req_i, output logic rd_gnt_o, - input logic [AxiAddrWidth-1:0] rd_addr_i, + input logic [CVA6Cfg.AxiAddrWidth-1:0] rd_addr_i, input logic [$clog2(AxiNumWords)-1:0] rd_blen_i, // axi convention: LEN-1 input logic [2:0] rd_size_i, - input logic [AxiIdWidth-1:0] rd_id_i, // use same ID for reads, or make sure you only have one outstanding read tx + input logic [CVA6Cfg.AxiIdWidth-1:0] rd_id_i, // use same ID for reads, or make sure you only have one outstanding read tx input logic rd_lock_i, // read response (we have to unconditionally sink the response) input logic rd_rdy_i, output logic rd_last_o, output logic rd_valid_o, - output logic [AxiDataWidth-1:0] rd_data_o, - output logic [AxiUserWidth-1:0] rd_user_o, - output logic [AxiIdWidth-1:0] rd_id_o, + output logic [CVA6Cfg.AxiDataWidth-1:0] rd_data_o, + output logic [CVA6Cfg.AxiUserWidth-1:0] rd_user_o, + output logic [CVA6Cfg.AxiIdWidth-1:0] rd_id_o, output logic rd_exokay_o, // indicates whether exclusive tx succeeded // write channel input logic wr_req_i, output logic wr_gnt_o, - input logic [AxiAddrWidth-1:0] wr_addr_i, - input logic [AxiNumWords-1:0][AxiDataWidth-1:0] wr_data_i, - input logic [AxiNumWords-1:0][AxiUserWidth-1:0] wr_user_i, - input logic [AxiNumWords-1:0][(AxiDataWidth/8)-1:0] wr_be_i, + input logic [CVA6Cfg.AxiAddrWidth-1:0] wr_addr_i, + input logic [AxiNumWords-1:0][CVA6Cfg.AxiDataWidth-1:0] wr_data_i, + input logic [AxiNumWords-1:0][CVA6Cfg.AxiUserWidth-1:0] wr_user_i, + input logic [AxiNumWords-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] wr_be_i, input logic [$clog2(AxiNumWords)-1:0] wr_blen_i, // axi convention: LEN-1 input logic [2:0] wr_size_i, - input logic [AxiIdWidth-1:0] wr_id_i, + input logic [CVA6Cfg.AxiIdWidth-1:0] wr_id_i, input logic wr_lock_i, input logic [5:0] wr_atop_i, // write response input logic wr_rdy_i, output logic wr_valid_o, - output logic [AxiIdWidth-1:0] wr_id_o, + output logic [CVA6Cfg.AxiIdWidth-1:0] wr_id_o, output logic wr_exokay_o, // indicates whether exclusive tx succeeded // AXI port output axi_req_t axi_req_o, @@ -87,7 +83,7 @@ module axi_shim #( // address assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction - assign axi_req_o.aw.addr = wr_addr_i[AxiAddrWidth-1:0]; + assign axi_req_o.aw.addr = wr_addr_i[CVA6Cfg.AxiAddrWidth-1:0]; assign axi_req_o.aw.size = wr_size_i; assign axi_req_o.aw.len = wr_blen_i; assign axi_req_o.aw.id = wr_id_i; @@ -246,7 +242,7 @@ module axi_shim #( // in case of a wrapping transfer we can simply begin at the address, if we want to request a cache-line // with an incremental transfer we need to output the corresponding base address of the cache line assign axi_req_o.ar.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction - assign axi_req_o.ar.addr = rd_addr_i[AxiAddrWidth-1:0]; + assign axi_req_o.ar.addr = rd_addr_i[CVA6Cfg.AxiAddrWidth-1:0]; assign axi_req_o.ar.size = rd_size_i; assign axi_req_o.ar.len = rd_blen_i; assign axi_req_o.ar.id = rd_id_i; @@ -297,7 +293,7 @@ module axi_shim #( initial begin assert (AxiNumWords >= 1) else $fatal(1, "[axi adapter] AxiNumWords must be >= 1"); - assert (AxiIdWidth >= 2) else + assert (CVA6Cfg.AxiIdWidth >= 2) else $fatal(1, "[axi adapter] AXI id width must be at least 2 bit wide"); end //pragma translate_on diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv index e5f7ed1c7..942cc64b9 100644 --- a/core/cache_subsystem/axi_adapter.sv +++ b/core/cache_subsystem/axi_adapter.sv @@ -21,38 +21,35 @@ module axi_adapter #( parameter int unsigned DATA_WIDTH = 256, parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature parameter int unsigned CACHELINE_BYTE_OFFSET = 8, - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_ID_WIDTH = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic req_i, - input ariane_axi::ad_req_t type_i, + input ariane_pkg::ad_req_t type_i, input ariane_pkg::amo_t amo_i, output logic gnt_o, input logic [riscv::XLEN-1:0] addr_i, input logic we_i, - input logic [(DATA_WIDTH/AXI_DATA_WIDTH)-1:0][AXI_DATA_WIDTH-1:0] wdata_i, - input logic [(DATA_WIDTH/AXI_DATA_WIDTH)-1:0][(AXI_DATA_WIDTH/8)-1:0] be_i, + input logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] wdata_i, + input logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] be_i, input logic [1:0] size_i, - input logic [AXI_ID_WIDTH-1:0] id_i, + input logic [CVA6Cfg.AxiIdWidth-1:0] id_i, // read port output logic valid_o, - output logic [(DATA_WIDTH/AXI_DATA_WIDTH)-1:0][AXI_DATA_WIDTH-1:0] rdata_o, - output logic [AXI_ID_WIDTH-1:0] id_o, + output logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] rdata_o, + output logic [CVA6Cfg.AxiIdWidth-1:0] id_o, // critical word - read port - output logic [AXI_DATA_WIDTH-1:0] critical_word_o, + output logic [CVA6Cfg.AxiDataWidth-1:0] critical_word_o, output logic critical_word_valid_o, // AXI port output axi_req_t axi_req_o, input axi_rsp_t axi_resp_i ); - localparam BURST_SIZE = (DATA_WIDTH/AXI_DATA_WIDTH)-1; - localparam ADDR_INDEX = ($clog2(DATA_WIDTH/AXI_DATA_WIDTH) > 0) ? $clog2(DATA_WIDTH/AXI_DATA_WIDTH) : 1; + localparam BURST_SIZE = (DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1; + localparam ADDR_INDEX = ($clog2(DATA_WIDTH/CVA6Cfg.AxiDataWidth) > 0) ? $clog2(DATA_WIDTH/CVA6Cfg.AxiDataWidth) : 1; enum logic [3:0] { IDLE, WAIT_B_VALID, WAIT_AW_READY, WAIT_LAST_W_READY, WAIT_LAST_W_READY_AW_READY, WAIT_AW_READY_BURST, @@ -61,10 +58,10 @@ module axi_adapter #( // counter for AXI transfers logic [ADDR_INDEX-1:0] cnt_d, cnt_q; - logic [(DATA_WIDTH/AXI_DATA_WIDTH)-1:0][AXI_DATA_WIDTH-1:0] cache_line_d, cache_line_q; + logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] cache_line_d, cache_line_q; // save the address for a read, as we allow for non-cacheline aligned accesses - logic [(DATA_WIDTH/AXI_DATA_WIDTH)-1:0] addr_offset_d, addr_offset_q; - logic [AXI_ID_WIDTH-1:0] id_d, id_q; + logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0] addr_offset_d, addr_offset_q; + logic [CVA6Cfg.AxiIdWidth-1:0] id_d, id_q; logic [ADDR_INDEX-1:0] index; // save the atomic operation and size ariane_pkg::amo_t amo_d, amo_q; @@ -92,7 +89,7 @@ module axi_adapter #( axi_req_o.ar.addr = addr_i; // in case of a single request or wrapping transfer we can simply begin at the address, if we want to request a cache-line // with an incremental transfer we need to output the corresponding base address of the cache line - if (!CRITICAL_WORD_FIRST && type_i != ariane_axi::SINGLE_REQ) begin + if (!CRITICAL_WORD_FIRST && type_i != ariane_pkg::SINGLE_REQ) begin axi_req_o.ar.addr[CACHELINE_BYTE_OFFSET-1:0] = '0; end axi_req_o.ar.prot = 3'b0; @@ -147,7 +144,7 @@ module axi_adapter #( // store-conditional requires exclusive access axi_req_o.aw.lock = amo_i == ariane_pkg::AMO_SC; // its a single write - if (type_i == ariane_axi::SINGLE_REQ) begin + if (type_i == ariane_pkg::SINGLE_REQ) begin // only a single write so the data is already the last one axi_req_o.w.last = 1'b1; // single req can be granted here @@ -194,7 +191,7 @@ module axi_adapter #( axi_req_o.ar.lock = amo_i == ariane_pkg::AMO_LR; gnt_o = axi_resp_i.ar_ready; - if (type_i != ariane_axi::SINGLE_REQ) begin + if (type_i != ariane_pkg::SINGLE_REQ) begin assert (amo_i == ariane_pkg::AMO_NONE) else $fatal("Bursts of atomic operations are not supported"); @@ -203,7 +200,7 @@ module axi_adapter #( end if (axi_resp_i.ar_ready) begin - state_d = (type_i == ariane_axi::SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE; + state_d = (type_i == ariane_pkg::SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE; addr_offset_d = addr_i[ADDR_INDEX-1+3:3]; end end @@ -226,7 +223,7 @@ module axi_adapter #( WAIT_LAST_W_READY_AW_READY: begin axi_req_o.w_valid = 1'b1; axi_req_o.w.last = (cnt_q == '0); - if (type_i == ariane_axi::SINGLE_REQ) begin + if (type_i == ariane_pkg::SINGLE_REQ) begin axi_req_o.w.data = wdata_i[0]; axi_req_o.w.strb = be_i[0]; end else begin @@ -278,7 +275,7 @@ module axi_adapter #( WAIT_LAST_W_READY: begin axi_req_o.w_valid = 1'b1; - if (type_i != ariane_axi::SINGLE_REQ) begin + if (type_i != ariane_pkg::SINGLE_REQ) begin axi_req_o.w.data = wdata_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q]; axi_req_o.w.strb = be_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q]; end diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index 22683a3b2..7c133c2b9 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -16,11 +16,8 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdWidth = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -40,8 +37,8 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( input axi_rsp_t axi_resp_i ); - localparam AxiNumWords = (ICACHE_LINE_WIDTH/AxiDataWidth) * (ICACHE_LINE_WIDTH > DCACHE_LINE_WIDTH) + - (DCACHE_LINE_WIDTH/AxiDataWidth) * (ICACHE_LINE_WIDTH <= DCACHE_LINE_WIDTH) ; + localparam AxiNumWords = (ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (ICACHE_LINE_WIDTH > DCACHE_LINE_WIDTH) + + (DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (ICACHE_LINE_WIDTH <= DCACHE_LINE_WIDTH) ; logic icache_mem_rtrn_vld; icache_rtrn_t icache_mem_rtrn; @@ -51,22 +48,22 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( logic axi_rd_req; logic axi_rd_gnt; - logic [AxiAddrWidth-1:0] axi_rd_addr; + logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr; logic [$clog2(AxiNumWords)-1:0] axi_rd_blen; logic [2:0] axi_rd_size; - logic [AxiIdWidth-1:0] axi_rd_id_in; + logic [CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_in; logic axi_rd_rdy; logic axi_rd_lock; logic axi_rd_last; logic axi_rd_valid; - logic [AxiDataWidth-1:0] axi_rd_data; - logic [AxiIdWidth-1:0] axi_rd_id_out; + logic [CVA6Cfg.AxiDataWidth-1:0] axi_rd_data; + logic [CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_out; logic axi_rd_exokay; logic req_valid_d, req_valid_q; icache_req_t req_data_d, req_data_q; logic first_d, first_q; - logic [ICACHE_LINE_WIDTH/AxiDataWidth-1:0][AxiDataWidth-1:0] rd_shift_d, rd_shift_q; + logic [ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] rd_shift_d, rd_shift_q; // Keep read request asserted until we have an AXI grant. This is not guaranteed by icache (but // required by AXI). @@ -77,11 +74,11 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( // We have a new or pending read request assign axi_rd_req = icache_mem_data_req | req_valid_q; - assign axi_rd_addr = AxiAddrWidth'(req_data_d.paddr); + assign axi_rd_addr = CVA6Cfg.AxiAddrWidth'(req_data_d.paddr); // Fetch a full cache line on a cache miss, or a single word on a bypassed access assign axi_rd_blen = (req_data_d.nc) ? '0 : ariane_pkg::ICACHE_LINE_WIDTH/64-1; - assign axi_rd_size = $clog2(AxiDataWidth/8); // Maximum + assign axi_rd_size = $clog2(CVA6Cfg.AxiDataWidth/8); // Maximum assign axi_rd_id_in = req_data_d.tid; assign axi_rd_rdy = 1'b1; assign axi_rd_lock = 1'b0; @@ -127,10 +124,6 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( axi_shim #( .CVA6Cfg ( CVA6Cfg ), .AxiNumWords ( AxiNumWords ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), - .AxiUserWidth ( AXI_USER_WIDTH ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_axi_shim ( @@ -176,10 +169,10 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( if (axi_rd_valid) begin first_d = axi_rd_last; - if (ICACHE_LINE_WIDTH == AxiDataWidth) begin + if (ICACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin rd_shift_d = axi_rd_data; end else begin - rd_shift_d = {axi_rd_data, rd_shift_q[ICACHE_LINE_WIDTH/AxiDataWidth-1:1]}; + rd_shift_d = {axi_rd_data, rd_shift_q[ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1]}; end // If this is a single word transaction, we need to make sure that word is placed at offset 0 diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index 7c2dd9a96..701ba0f67 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -19,11 +19,8 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter int unsigned NR_PORTS = 3, - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_ID_WIDTH = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic )( input logic clk_i, input logic rst_ni, @@ -122,7 +119,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( logic [DCACHE_LINE_WIDTH-1:0] req_fsm_miss_wdata; logic req_fsm_miss_we; logic [(DCACHE_LINE_WIDTH/8)-1:0] req_fsm_miss_be; - ariane_axi::ad_req_t req_fsm_miss_req; + ariane_pkg::ad_req_t req_fsm_miss_req; logic [1:0] req_fsm_miss_size; logic gnt_miss_fsm; @@ -167,11 +164,11 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( req_fsm_miss_wdata = '0; req_fsm_miss_we = 1'b0; req_fsm_miss_be = '0; - req_fsm_miss_req = ariane_axi::CACHE_LINE_REQ; + req_fsm_miss_req = ariane_pkg::CACHE_LINE_REQ; req_fsm_miss_size = 2'b11; // to AXI bypass amo_bypass_req.req = 1'b0; - amo_bypass_req.reqtype = ariane_axi::SINGLE_REQ; + amo_bypass_req.reqtype = ariane_pkg::SINGLE_REQ; amo_bypass_req.amo = ariane_pkg::AMO_NONE; amo_bypass_req.addr = '0; amo_bypass_req.we = 1'b0; @@ -401,7 +398,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( // ~> we are here because we need to do the AMO, the cache is clean at this point AMO_REQ: begin amo_bypass_req.req = 1'b1; - amo_bypass_req.reqtype = ariane_axi::SINGLE_REQ; + amo_bypass_req.reqtype = ariane_pkg::SINGLE_REQ; amo_bypass_req.amo = amo_req_i.amo_op; // address is in operand a amo_bypass_req.addr = amo_req_i.operand_a; @@ -525,7 +522,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( // Pack MHSR ports first for (id = 0; id < NR_PORTS; id++) begin bypass_ports_req[id].req = miss_req_valid[id] & miss_req_bypass[id]; - bypass_ports_req[id].reqtype = ariane_axi::SINGLE_REQ; + bypass_ports_req[id].reqtype = ariane_pkg::SINGLE_REQ; bypass_ports_req[id].amo = AMO_NONE; bypass_ports_req[id].id = {2'b10, id}; bypass_ports_req[id].addr = miss_req_addr[id]; @@ -573,9 +570,6 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( .CVA6Cfg ( CVA6Cfg ), .DATA_WIDTH ( 64 ), .CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_bypass_axi_adapter ( @@ -584,7 +578,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( .req_i (bypass_adapter_req.req), .type_i (bypass_adapter_req.reqtype), .amo_i (bypass_adapter_req.amo), - .id_i (({{AXI_ID_WIDTH-4{1'b0}}, bypass_adapter_req.id})), + .id_i (({{CVA6Cfg.AxiIdWidth-4{1'b0}}, bypass_adapter_req.id})), .addr_i (bypass_addr), .wdata_i (bypass_adapter_req.wdata), .we_i (bypass_adapter_req.we), @@ -611,9 +605,6 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( .CVA6Cfg ( CVA6Cfg ), .DATA_WIDTH ( DCACHE_LINE_WIDTH ), .CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_miss_axi_adapter ( @@ -628,7 +619,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( .wdata_i ( req_fsm_miss_wdata ), .be_i ( req_fsm_miss_be ), .size_i ( req_fsm_miss_size ), - .id_i ( {{AXI_ID_WIDTH-4{1'b0}}, 4'b1100} ), + .id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b1100} ), .valid_o ( valid_miss_fsm ), .rdata_o ( data_miss_fsm ), .id_o ( ), diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 221e77d73..fadbd8d07 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -18,14 +18,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdWidth = 0, - parameter type axi_ar_chan_t = ariane_axi::ar_chan_t, - parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, - parameter type axi_w_chan_t = ariane_axi::w_chan_t, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_ar_chan_t = logic, + parameter type axi_aw_chan_t = logic, + parameter type axi_w_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -70,9 +67,6 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( cva6_icache_axi_wrapper #( .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_cva6_icache_axi_wrapper ( @@ -97,9 +91,6 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( std_nbdcache #( .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ), - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidth ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_nbdcache ( diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index 245771075..a9fdf4115 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -16,11 +16,8 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_ID_WIDTH = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -136,9 +133,6 @@ import std_cache_pkg::*; miss_handler #( .CVA6Cfg ( CVA6Cfg ), .NR_PORTS ( 3 ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_miss_handler ( @@ -275,7 +269,7 @@ import std_cache_pkg::*; //pragma translate_off initial begin - assert (DCACHE_LINE_WIDTH/AXI_DATA_WIDTH inside {2, 4, 8, 16}) else $fatal(1, "Cache line size needs to be a power of two multiple of AXI_DATA_WIDTH"); + assert (DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth inside {2, 4, 8, 16}) else $fatal(1, "Cache line size needs to be a power of two multiple of AxiDataWidth"); end //pragma translate_on endmodule diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index cea52e1f2..cc90d63d9 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -18,11 +18,8 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter int unsigned ReqFifoDepth = 2, parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX, - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdWidth = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -54,8 +51,8 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( ); // support up to 512bit cache lines - localparam AxiNumWords = (ariane_pkg::ICACHE_LINE_WIDTH/AxiDataWidth) * (ariane_pkg::ICACHE_LINE_WIDTH > ariane_pkg::DCACHE_LINE_WIDTH) + - (ariane_pkg::DCACHE_LINE_WIDTH/AxiDataWidth) * (ariane_pkg::ICACHE_LINE_WIDTH <= ariane_pkg::DCACHE_LINE_WIDTH) ; + localparam AxiNumWords = (ariane_pkg::ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (ariane_pkg::ICACHE_LINE_WIDTH > ariane_pkg::DCACHE_LINE_WIDTH) + + (ariane_pkg::DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (ariane_pkg::ICACHE_LINE_WIDTH <= ariane_pkg::DCACHE_LINE_WIDTH) ; /////////////////////////////////////////////////////// @@ -74,18 +71,18 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( logic axi_wr_req, axi_wr_gnt; logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy; logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay; - logic [AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr; + logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr; logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; logic [2:0] axi_rd_size, axi_wr_size; - logic [AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out; - logic [AxiNumWords-1:0][AxiDataWidth-1:0] axi_wr_data; - logic [AxiNumWords-1:0][AXI_USER_WIDTH-1:0] axi_wr_user; - logic [AxiDataWidth-1:0] axi_rd_data; - logic [AXI_USER_WIDTH-1:0] axi_rd_user; - logic [AxiNumWords-1:0][(AxiDataWidth/8)-1:0] axi_wr_be; + logic [CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out; + logic [AxiNumWords-1:0][CVA6Cfg.AxiDataWidth-1:0] axi_wr_data; + logic [AxiNumWords-1:0][CVA6Cfg.AxiUserWidth-1:0] axi_wr_user; + logic [CVA6Cfg.AxiDataWidth-1:0] axi_rd_data; + logic [CVA6Cfg.AxiUserWidth-1:0] axi_rd_user; + logic [AxiNumWords-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] axi_wr_be; logic [5:0] axi_wr_atop; logic invalidate; - logic [$clog2(AxiDataWidth/8)-1:0] amo_off_d, amo_off_q; + logic [$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] amo_off_d, amo_off_q; // AMO generates r beat logic amo_gen_r_d, amo_gen_r_q; @@ -132,7 +129,7 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( always_comb begin : p_axi_req // write channel axi_wr_id_in = arb_idx; - axi_wr_data = {(AxiDataWidth/riscv::XLEN){dcache_data.data}}; + axi_wr_data = {(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}}; axi_wr_user = dcache_data.user; // Cast to AXI address width axi_wr_addr = dcache_data.paddr; @@ -152,9 +149,9 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( axi_rd_blen = '0; if (dcache_data.paddr[2] == 1'b0) begin - axi_wr_user = {{64-AXI_USER_WIDTH{1'b0}}, dcache_data.user}; + axi_wr_user = {{64-CVA6Cfg.AxiUserWidth{1'b0}}, dcache_data.user}; end else begin - axi_wr_user = {dcache_data.user, {64-AXI_USER_WIDTH{1'b0}}}; + axi_wr_user = {dcache_data.user, {64-CVA6Cfg.AxiUserWidth{1'b0}}}; end // arbiter mux @@ -162,16 +159,16 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( // Cast to AXI address width axi_rd_addr = dcache_data.paddr; // If dcache_data.size MSB is set, we want to read as much as possible - axi_rd_size = dcache_data.size[2] ? $clog2(AxiDataWidth/8) : dcache_data.size; + axi_rd_size = dcache_data.size[2] ? $clog2(CVA6Cfg.AxiDataWidth/8) : dcache_data.size; if (dcache_data.size[2]) begin - axi_rd_blen = ariane_pkg::DCACHE_LINE_WIDTH/AxiDataWidth-1; + axi_rd_blen = ariane_pkg::DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1; end end else begin // Cast to AXI address width axi_rd_addr = icache_data.paddr; - axi_rd_size = $clog2(AxiDataWidth/8); // always request max number of words in case of ifill + axi_rd_size = $clog2(CVA6Cfg.AxiDataWidth/8); // always request max number of words in case of ifill if (!icache_data.nc) begin - axi_rd_blen = ariane_pkg::ICACHE_LINE_WIDTH/AxiDataWidth-1; + axi_rd_blen = ariane_pkg::ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1; end end @@ -197,10 +194,10 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( axi_wr_req = 1'b1; axi_wr_be = '0; unique case(dcache_data.size[1:0]) - 2'b00: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0]] = '1; // byte - 2'b01: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] +:2 ] = '1; // hword - 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] +:4 ] = '1; // word - default: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] +:8 ] = '1; // dword = '1; // dword + 2'b00: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte + 2'b01: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:2 ] = '1; // hword + 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:4 ] = '1; // word + default: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:8 ] = '1; // dword endcase end ////////////////////////////////////// @@ -214,10 +211,10 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( axi_wr_req = 1'b1; axi_wr_be = '0; unique case(dcache_data.size[1:0]) - 2'b00: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0]] = '1; // byte - 2'b01: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] +:2 ] = '1; // hword - 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] +:4 ] = '1; // word - default: axi_wr_be[0][dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] +:8 ] = '1; // dword + 2'b00: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte + 2'b01: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:2 ] = '1; // hword + 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:4 ] = '1; // word + default: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:8 ] = '1; // dword endcase amo_gen_r_d = 1'b1; // need to use a separate ID here, so concat an additional bit @@ -237,15 +234,15 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( amo_gen_r_d = 1'b0; // needed to properly encode success. store the result at offset within the returned // AXI data word aligned with the requested word size. - amo_off_d = dcache_data.paddr[$clog2(AxiDataWidth/8)-1:0] & ~((1 << dcache_data.size[1:0]) - 1); + amo_off_d = dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] & ~((1 << dcache_data.size[1:0]) - 1); end // RISC-V atops have a load semantic AMO_SWAP: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ATOMICSWAP}; AMO_ADD: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; AMO_AND: begin // in this case we need to invert the data to get a "CLR" - axi_wr_data = ~{(AxiDataWidth/riscv::XLEN){dcache_data.data}}; - axi_wr_user = ~{(AxiDataWidth/riscv::XLEN){dcache_data.user}}; + axi_wr_data = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}}; + axi_wr_user = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.user}}; axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}; end AMO_OR: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}; @@ -369,7 +366,7 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( assign b_push = axi_wr_valid & axi_wr_rdy; fifo_v3 #( - .DATA_WIDTH ( AxiIdWidth + 1 ), + .DATA_WIDTH ( CVA6Cfg.AxiIdWidth + 1 ), .DEPTH ( MetaFifoDepth ), .FALL_THROUGH ( 1'b1 ) ) i_b_fifo ( @@ -388,10 +385,10 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( // buffer read responses in shift regs logic icache_first_d, icache_first_q, dcache_first_d, dcache_first_q; - logic [ICACHE_USER_LINE_WIDTH/AXI_USER_WIDTH-1:0][AXI_USER_WIDTH-1:0] icache_rd_shift_user_d, icache_rd_shift_user_q; - logic [DCACHE_USER_LINE_WIDTH/AXI_USER_WIDTH-1:0][AXI_USER_WIDTH-1:0] dcache_rd_shift_user_d, dcache_rd_shift_user_q; - logic [ICACHE_LINE_WIDTH/AxiDataWidth-1:0][AxiDataWidth-1:0] icache_rd_shift_d, icache_rd_shift_q; - logic [DCACHE_LINE_WIDTH/AxiDataWidth-1:0][AxiDataWidth-1:0] dcache_rd_shift_d, dcache_rd_shift_q; + logic [ICACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:0][CVA6Cfg.AxiUserWidth-1:0] icache_rd_shift_user_d, icache_rd_shift_user_q; + logic [DCACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:0][CVA6Cfg.AxiUserWidth-1:0] dcache_rd_shift_user_d, dcache_rd_shift_user_q; + logic [ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] icache_rd_shift_d, icache_rd_shift_q; + logic [DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] dcache_rd_shift_d, dcache_rd_shift_q; wt_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q; wt_cache_pkg::dcache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q; logic dcache_sc_rtrn, axi_rd_last; @@ -423,12 +420,12 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( if (icache_rtrn_rd_en) begin icache_first_d = axi_rd_last; - if (ICACHE_LINE_WIDTH == AxiDataWidth) begin + if (ICACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin icache_rd_shift_d = axi_rd_data; end else begin - icache_rd_shift_d = {axi_rd_data, icache_rd_shift_q[ICACHE_LINE_WIDTH/AxiDataWidth-1:1]}; + icache_rd_shift_d = {axi_rd_data, icache_rd_shift_q[ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1]}; end - icache_rd_shift_user_d = {axi_rd_user, icache_rd_shift_user_q[ICACHE_USER_LINE_WIDTH/AXI_USER_WIDTH-1:1]}; + icache_rd_shift_user_d = {axi_rd_user, icache_rd_shift_user_q[ICACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:1]}; // if this is a single word transaction, we need to make sure that word is placed at offset 0 if (icache_first_q) begin icache_rd_shift_d[0] = axi_rd_data; @@ -438,12 +435,12 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( if (dcache_rtrn_rd_en) begin dcache_first_d = axi_rd_last; - if (DCACHE_LINE_WIDTH == AxiDataWidth) begin + if (DCACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin dcache_rd_shift_d = axi_rd_data; end else begin - dcache_rd_shift_d = {axi_rd_data, dcache_rd_shift_q[DCACHE_LINE_WIDTH/AxiDataWidth-1:1]}; + dcache_rd_shift_d = {axi_rd_data, dcache_rd_shift_q[DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1]}; end - dcache_rd_shift_user_d = {axi_rd_user, dcache_rd_shift_user_q[DCACHE_USER_LINE_WIDTH/AXI_USER_WIDTH-1:1]}; + dcache_rd_shift_user_d = {axi_rd_user, dcache_rd_shift_user_q[DCACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:1]}; // if this is a single word transaction, we need to make sure that word is placed at offset 0 if (dcache_first_q) begin dcache_rd_shift_d[0] = axi_rd_data; @@ -608,10 +605,6 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( axi_shim #( .CVA6Cfg ( CVA6Cfg ), .AxiNumWords ( AxiNumWords ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), - .AxiUserWidth ( AXI_USER_WIDTH ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_axi_shim ( diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index 1123a36f6..7d35dd4e6 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -23,11 +23,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions parameter int unsigned NumPorts = 3, - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdWidth = 0, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type noc_req_t = logic, + parameter type noc_resp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -58,15 +55,9 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( // writebuffer status output logic wbuffer_empty_o, output logic wbuffer_not_ni_o, -`ifdef PITON_ARIANE - // L15 (memory side) - output l15_req_t l15_req_o, - input l15_rtrn_t l15_rtrn_i, -`else // memory side - output axi_req_t axi_req_o, - input axi_rsp_t axi_resp_i, -`endif + output noc_req_t noc_req_o, + input noc_resp_t noc_resp_i, // Invalidations input logic [63:0] inval_addr_i, input logic inval_valid_i, @@ -112,7 +103,6 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( // Port 2 is write only and goes into the merging write buffer wt_dcache #( .CVA6Cfg ( CVA6Cfg ), - .AxiDataWidth ( AxiDataWidth ), // use ID 1 for dcache reads and amos. note that the writebuffer // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. .RdAmoTxId ( 1 ), @@ -161,17 +151,14 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( .dcache_data_i ( dcache_adapter ), .dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ), .dcache_rtrn_o ( adapter_dcache ), - .l15_req_o ( l15_req_o ), - .l15_rtrn_i ( l15_rtrn_i ) + .l15_req_o ( noc_req_o ), + .l15_rtrn_i ( noc_resp_i ) ); `else wt_axi_adapter #( .CVA6Cfg ( CVA6Cfg ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .axi_req_t ( noc_req_t ), + .axi_rsp_t ( noc_resp_t ) ) i_adapter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -185,8 +172,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( .dcache_data_i ( dcache_adapter ), .dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ), .dcache_rtrn_o ( adapter_dcache ), - .axi_req_o ( axi_req_o ), - .axi_resp_i ( axi_resp_i ), + .axi_req_o ( noc_req_o ), + .axi_resp_i ( noc_resp_i ), .inval_addr_i ( inval_addr_i ), .inval_valid_i ( inval_valid_i ), .inval_ready_o ( inval_ready_o ) diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index 8b96b1bb3..9244817ca 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -15,7 +15,6 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, - parameter int unsigned AxiDataWidth = 0, parameter int unsigned NumPorts = 3, // number of miss ports // ID to be used for read and AMO transactions. // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions @@ -116,8 +115,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( .CVA6Cfg ( CVA6Cfg ), .AxiCompliant ( ArianeCfg.AxiCompliant ), .AmoTxId ( RdAmoTxId ), - .NumPorts ( NumPorts ), - .AxiDataWidth ( AxiDataWidth ) + .NumPorts ( NumPorts ) ) i_wt_dcache_missunit ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -282,7 +280,6 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( wt_dcache_mem #( .CVA6Cfg ( CVA6Cfg ), .AxiCompliant ( ArianeCfg.AxiCompliant ), - .AxiDataWidth ( AxiDataWidth ), .NumPorts ( NumPorts ) ) i_wt_dcache_mem ( .clk_i ( clk_i ), diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv index 77e199eca..d25a590ad 100644 --- a/core/cache_subsystem/wt_dcache_mem.sv +++ b/core/cache_subsystem/wt_dcache_mem.sv @@ -29,7 +29,6 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter - parameter int unsigned AxiDataWidth = 0, parameter int unsigned NumPorts = 3 ) ( input logic clk_i, @@ -85,7 +84,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( // number of bits needed to address AXI data. If AxiDataWidth equals XLEN this parameter // is not needed. Therefore, increment it by one to avoid reverse range select during elaboration. - localparam AXI_OFFSET_WIDTH = AxiDataWidth == riscv::XLEN ? $clog2(AxiDataWidth/8)+1 : $clog2(AxiDataWidth/8); + localparam AXI_OFFSET_WIDTH = CVA6Cfg.AxiDataWidth == riscv::XLEN ? $clog2(CVA6Cfg.AxiDataWidth/8)+1 : $clog2(CVA6Cfg.AxiDataWidth/8); logic [DCACHE_NUM_BANKS-1:0] bank_req; logic [DCACHE_NUM_BANKS-1:0] bank_we; @@ -259,7 +258,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( if (AxiCompliant) begin : gen_axi_off // In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read - assign wr_cl_off = (wr_cl_nc_i) ? (AxiDataWidth == riscv::XLEN) ? '0 : + assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 : wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES] : wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES]; end else begin : gen_piton_off @@ -356,12 +355,12 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( //pragma translate_off `ifndef VERILATOR initial begin - cach_line_width_axi: assert (DCACHE_LINE_WIDTH >= AxiDataWidth) + cach_line_width_axi: assert (DCACHE_LINE_WIDTH >= CVA6Cfg.AxiDataWidth) else $fatal(1, "[l1 dcache] cache line size needs to be greater or equal AXI data width"); end initial begin - axi_xlen: assert (AxiDataWidth >= riscv::XLEN) + axi_xlen: assert (CVA6Cfg.AxiDataWidth >= riscv::XLEN) else $fatal(1, "[l1 dcache] AXI data width needs to be greater or equal XLEN"); end diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index fa1f7f029..4fa09c4e6 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -18,8 +18,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty, parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs - parameter int unsigned NumPorts = 3, // number of miss ports - parameter int AxiDataWidth = 0 + parameter int unsigned NumPorts = 3 // number of miss ports ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -257,8 +256,8 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #( // note: openpiton returns a full cacheline! if (AxiCompliant) begin : gen_axi_rtrn_mux - if (AxiDataWidth > 64) begin - assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(AxiDataWidth/8)-1:3]*64 +: 64]; + if (CVA6Cfg.AxiDataWidth > 64) begin + assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(CVA6Cfg.AxiDataWidth/8)-1:3]*64 +: 64]; end else begin assign amo_rtrn_mux = mem_rtrn_i.data[0 +: 64]; end diff --git a/core/cva6.sv b/core/cva6.sv index 741b3727e..0f3300cd6 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -15,8 +15,12 @@ module cva6 import ariane_pkg::*; #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = { - int'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - int'(cva6_config_pkg::CVA6ConfigRvfiTrace) // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(cva6_config_pkg::CVA6ConfigRvfiTrace), // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // AxiUserWidth }, parameter type rvfi_instr_t = struct packed { logic [ariane_pkg::NRET-1:0] valid; @@ -43,18 +47,75 @@ module cva6 import ariane_pkg::*; #( logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata; logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }, + // AXI types + parameter type axi_ar_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + logic [CVA6Cfg.AxiAddrWidth-1:0] addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + logic lock; + axi_pkg::cache_t cache; + axi_pkg::prot_t prot; + axi_pkg::qos_t qos; + axi_pkg::region_t region; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type axi_aw_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + logic [CVA6Cfg.AxiAddrWidth-1:0] addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + logic lock; + axi_pkg::cache_t cache; + axi_pkg::prot_t prot; + axi_pkg::qos_t qos; + axi_pkg::region_t region; + axi_pkg::atop_t atop; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type axi_w_chan_t = struct packed { + logic [CVA6Cfg.AxiDataWidth-1:0] data; + logic [(CVA6Cfg.AxiDataWidth/8)-1:0] strb; + logic last; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type b_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + axi_pkg::resp_t resp; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type r_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + logic [CVA6Cfg.AxiDataWidth-1:0] data; + axi_pkg::resp_t resp; + logic last; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type noc_req_t = struct packed { + axi_aw_chan_t aw; + logic aw_valid; + axi_w_chan_t w; + logic w_valid; + logic b_ready; + axi_ar_chan_t ar; + logic ar_valid; + logic r_ready; + }, + parameter type noc_resp_t = struct packed { + logic aw_ready; + logic ar_ready; + logic w_ready; + logic b_valid; + b_chan_t b; + logic r_valid; + r_chan_t r; + }, // parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, parameter type cvxif_req_t = cvxif_pkg::cvxif_req_t, - parameter type cvxif_resp_t = cvxif_pkg::cvxif_resp_t, - parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth, - parameter int unsigned AxiDataWidth = ariane_axi::DataWidth, - parameter int unsigned AxiIdWidth = ariane_axi::IdWidth, - parameter type axi_ar_chan_t = ariane_axi::ar_chan_t, - parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, - parameter type axi_w_chan_t = ariane_axi::w_chan_t, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type cvxif_resp_t = cvxif_pkg::cvxif_resp_t ) ( input logic clk_i, input logic rst_ni, @@ -72,12 +133,9 @@ module cva6 import ariane_pkg::*; #( output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, output cvxif_req_t cvxif_req_o, input cvxif_resp_t cvxif_resp_i, - // L15 (memory side) - output wt_cache_pkg::l15_req_t l15_req_o, - input wt_cache_pkg::l15_rtrn_t l15_rtrn_i, - // memory side, AXI Master - output axi_req_t axi_req_o, - input axi_rsp_t axi_resp_i + // memory side + output noc_req_t noc_req_o, + input noc_resp_t noc_resp_i ); // ------------------------------------------ @@ -773,11 +831,8 @@ module cva6 import ariane_pkg::*; #( .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ), .NumPorts ( NumPorts ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .noc_req_t ( noc_req_t ), + .noc_resp_t ( noc_resp_t ) ) i_cache_subsystem ( // to D$ .clk_i ( clk_i ), @@ -805,14 +860,9 @@ module cva6 import ariane_pkg::*; #( // write buffer status .wbuffer_empty_o ( dcache_commit_wbuffer_empty ), .wbuffer_not_ni_o ( dcache_commit_wbuffer_not_ni ), -`ifdef PITON_ARIANE - .l15_req_o ( l15_req_o ), - .l15_rtrn_i ( l15_rtrn_i ), -`else // memory side - .axi_req_o ( axi_req_o ), - .axi_resp_i ( axi_resp_i ), -`endif + .noc_req_o ( noc_req_o ), + .noc_resp_i ( noc_resp_i ), .inval_addr_i ( inval_addr ), .inval_valid_i ( inval_valid ), .inval_ready_o ( inval_ready ) @@ -825,14 +875,11 @@ module cva6 import ariane_pkg::*; #( // deprecated .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), .axi_ar_chan_t ( axi_ar_chan_t ), .axi_aw_chan_t ( axi_aw_chan_t ), .axi_w_chan_t ( axi_w_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .axi_req_t ( noc_req_t ), + .axi_rsp_t ( noc_resp_t ) ) i_cache_subsystem ( // to D$ .clk_i ( clk_i ), @@ -860,8 +907,8 @@ module cva6 import ariane_pkg::*; #( .dcache_req_ports_i ( dcache_req_ports_ex_cache ), .dcache_req_ports_o ( dcache_req_ports_cache_ex ), // memory side - .axi_req_o ( axi_req_o ), - .axi_resp_i ( axi_resp_i ) + .axi_req_o ( noc_req_o ), + .axi_resp_i ( noc_resp_i ) ); assign dcache_commit_wbuffer_not_ni = 1'b1; assign inval_ready = 1'b1; diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 505bb04f5..720615191 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -37,11 +37,19 @@ package ariane_pkg; typedef struct packed { int unsigned NrCommitPorts; int unsigned IsRVFI; + int unsigned AxiAddrWidth; + int unsigned AxiDataWidth; + int unsigned AxiIdWidth; + int unsigned AxiUserWidth; } cva6_cfg_t; localparam cva6_cfg_t cva6_cfg_empty = { unsigned'(0), // NrCommitPorts - unsigned'(0) // IsRVFI + unsigned'(0), // IsRVFI + unsigned'(0), // AxiAddrWidth + unsigned'(0), // AxiDataWidth + unsigned'(0), // AxiIdWidth + unsigned'(0) // AxiUserWidth }; localparam NrMaxRules = 16; @@ -302,9 +310,6 @@ package ariane_pkg; // AXI // --------------- - localparam AXI_ID_WIDTH = cva6_config_pkg::CVA6ConfigAxiIdWidth; - localparam AXI_ADDR_WIDTH = cva6_config_pkg::CVA6ConfigAxiAddrWidth; - localparam AXI_DATA_WIDTH = cva6_config_pkg::CVA6ConfigAxiDataWidth; localparam FETCH_USER_WIDTH = cva6_config_pkg::CVA6ConfigFetchUserWidth; localparam DATA_USER_WIDTH = cva6_config_pkg::CVA6ConfigDataUserWidth; localparam AXI_USER_EN = cva6_config_pkg::CVA6ConfigDataUserEn | cva6_config_pkg::CVA6ConfigFetchUserEn; @@ -312,6 +317,8 @@ package ariane_pkg; localparam DATA_USER_EN = cva6_config_pkg::CVA6ConfigDataUserEn; localparam FETCH_USER_EN = cva6_config_pkg::CVA6ConfigFetchUserEn; + typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } ad_req_t; + // --------------- // Fetch Stage // --------------- diff --git a/core/include/std_cache_pkg.sv b/core/include/std_cache_pkg.sv index 3da4ba812..48532e7c0 100644 --- a/core/include/std_cache_pkg.sv +++ b/core/include/std_cache_pkg.sv @@ -44,7 +44,7 @@ package std_cache_pkg; typedef struct packed { logic req; - ariane_axi::ad_req_t reqtype; + ariane_pkg::ad_req_t reqtype; ariane_pkg::amo_t amo; logic [3:0] id; logic [63:0] addr; diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index b9bc0f053..405a56688 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -155,9 +155,13 @@ module ariane_xilinx ( ); // cva6 configuration -parameter ariane_pkg::cva6_cfg_t CVA6Cfg = { - int'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - int'(0) // IsRVFI +localparam ariane_pkg::cva6_cfg_t CVA6Cfg = { + unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(0), // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // DataUserWidth }; localparam type rvfi_instr_t = logic; @@ -569,17 +573,15 @@ logic [1:0] axi_adapter_size; assign axi_adapter_size = (riscv::XLEN == 64) ? 2'b11 : 2'b10; axi_adapter #( + .CVA6Cfg ( CVA6Cfg ), .DATA_WIDTH ( riscv::XLEN ), - .AXI_ADDR_WIDTH ( ariane_axi::AddrWidth ), - .AXI_DATA_WIDTH ( ariane_axi::DataWidth ), - .AXI_ID_WIDTH ( ariane_axi::IdWidth ), .axi_req_t ( ariane_axi::req_t ), .axi_rsp_t ( ariane_axi::resp_t ) ) i_dm_axi_master ( .clk_i ( clk ), .rst_ni ( rst_n ), .req_i ( dm_master_req ), - .type_i ( ariane_axi::SINGLE_REQ ), + .type_i ( ariane_pkg::SINGLE_REQ ), .amo_i ( ariane_pkg::AMO_NONE ), .gnt_o ( dm_master_gnt ), .addr_i ( dm_master_add ), @@ -719,8 +721,8 @@ ariane #( .ipi_i ( ipi ), .time_irq_i ( timer_irq ), .debug_req_i ( debug_req_irq ), - .axi_req_o ( axi_ariane_req ), - .axi_resp_i ( axi_ariane_resp ) + .noc_req_o ( axi_ariane_req ), + .noc_resp_i ( axi_ariane_resp ) ); `AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req) diff --git a/corev_apu/openpiton/ariane_verilog_wrap.sv b/corev_apu/openpiton/ariane_verilog_wrap.sv index 6979a88ca..5b8e57442 100644 --- a/corev_apu/openpiton/ariane_verilog_wrap.sv +++ b/corev_apu/openpiton/ariane_verilog_wrap.sv @@ -52,32 +52,18 @@ module ariane_verilog_wrap input time_irq_i, // timer interrupt in (async) input debug_req_i, // debug request (async) -`ifdef PITON_ARIANE // L15 (memory side) output [$size(wt_cache_pkg::l15_req_t)-1:0] l15_req_o, input [$size(wt_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i -`else - // AXI (memory side) - output [$size(ariane_axi::req_t)-1:0] axi_req_o, - input [$size(ariane_axi::resp_t)-1:0] axi_resp_i -`endif ); // assign bitvector to packed struct and vice versa -`ifdef PITON_ARIANE // L15 (memory side) wt_cache_pkg::l15_req_t l15_req; wt_cache_pkg::l15_rtrn_t l15_rtrn; assign l15_req_o = l15_req; assign l15_rtrn = l15_rtrn_i; -`else - ariane_axi::req_t axi_req; - ariane_axi::resp_t axi_resp; - - assign axi_req_o = axi_req; - assign axi_resp = axi_resp_i; -`endif ///////////////////////////// @@ -194,7 +180,9 @@ module ariane_verilog_wrap }; ariane #( - .ArianeCfg ( ArianeOpenPitonCfg ) + .ArianeCfg ( ArianeOpenPitonCfg ), + .noc_req_t ( wt_cache_pkg::l15_req_t ), + .noc_resp_t ( wt_cache_pkg::l15_rtrn_t ) ) ariane ( .clk_i ( clk_i ), .rst_ni ( spc_grst_l ), @@ -204,13 +192,8 @@ module ariane_verilog_wrap .ipi_i ( ipi ), .time_irq_i ( time_irq ), .debug_req_i ( debug_req ), -`ifdef PITON_ARIANE - .l15_req_o ( l15_req ), - .l15_rtrn_i ( l15_rtrn ) -`else - .axi_req_o ( axi_req ), - .axi_resp_i ( axi_resp ) -`endif + .noc_req_o ( l15_req ), + .noc_resp_i ( l15_rtrn ) ); endmodule // ariane_verilog_wrap diff --git a/corev_apu/src/ariane.sv b/corev_apu/src/ariane.sv index 4899da32b..cc6634578 100644 --- a/corev_apu/src/ariane.sv +++ b/corev_apu/src/ariane.sv @@ -24,8 +24,8 @@ module ariane import ariane_pkg::*; #( parameter type axi_ar_chan_t = ariane_axi::ar_chan_t, parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, parameter type axi_w_chan_t = ariane_axi::w_chan_t, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type noc_req_t = ariane_axi::req_t, + parameter type noc_resp_t = ariane_axi::resp_t ) ( input logic clk_i, input logic rst_ni, @@ -42,15 +42,9 @@ module ariane import ariane_pkg::*; #( // RISC-V formal interface port (`rvfi`): // Can be left open when formal tracing is not needed. output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, -`ifdef PITON_ARIANE - // L15 (memory side) - output wt_cache_pkg::l15_req_t l15_req_o, - input wt_cache_pkg::l15_rtrn_t l15_rtrn_i -`else - // memory side, AXI Master - output axi_req_t axi_req_o, - input axi_rsp_t axi_resp_i -`endif + // memory side + output noc_req_t noc_req_o, + input noc_resp_t noc_resp_i ); cvxif_pkg::cvxif_req_t cvxif_req; @@ -61,14 +55,11 @@ module ariane import ariane_pkg::*; #( .rvfi_instr_t ( rvfi_instr_t ), // .ArianeCfg ( ArianeCfg ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidth ( AxiIdWidth ), .axi_ar_chan_t (axi_ar_chan_t), .axi_aw_chan_t (axi_aw_chan_t), .axi_w_chan_t (axi_w_chan_t), - .axi_req_t (axi_req_t), - .axi_rsp_t (axi_rsp_t) + .noc_req_t (noc_req_t), + .noc_resp_t (noc_resp_t) ) i_cva6 ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -81,17 +72,8 @@ module ariane import ariane_pkg::*; #( .rvfi_o ( rvfi_o ), .cvxif_req_o ( cvxif_req ), .cvxif_resp_i ( cvxif_resp ), -`ifdef PITON_ARIANE - .l15_req_o ( l15_req_o ), - .l15_rtrn_i ( l15_rtrn_i ), - .axi_req_o ( ), - .axi_resp_i ( '0 ) -`else - .l15_req_o ( ), - .l15_rtrn_i ( '0 ), - .axi_req_o ( axi_req_o ), - .axi_resp_i ( axi_resp_i ) -`endif + .noc_req_o ( noc_req_o ), + .noc_resp_i ( noc_resp_i ) ); if (ariane_pkg::CVXIF_PRESENT) begin : gen_example_coprocessor diff --git a/core/include/ariane_axi_pkg.sv b/corev_apu/tb/ariane_axi_pkg.sv similarity index 89% rename from core/include/ariane_axi_pkg.sv rename to corev_apu/tb/ariane_axi_pkg.sv index 41b52bd0f..c750336ae 100644 --- a/core/include/ariane_axi_pkg.sv +++ b/corev_apu/tb/ariane_axi_pkg.sv @@ -17,13 +17,10 @@ package ariane_axi; - // used in axi_adapter.sv - typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } ad_req_t; - - localparam IdWidth = ariane_pkg::AXI_ID_WIDTH; // Recommended by AXI standard - localparam UserWidth = ariane_pkg::AXI_USER_WIDTH; - localparam AddrWidth = ariane_pkg::AXI_ADDR_WIDTH; - localparam DataWidth = ariane_pkg::AXI_DATA_WIDTH; + localparam IdWidth = cva6_config_pkg::CVA6ConfigAxiIdWidth; // Recommended by AXI standard + localparam UserWidth = cva6_config_pkg::CVA6ConfigDataUserWidth; + localparam AddrWidth = cva6_config_pkg::CVA6ConfigAxiAddrWidth; + localparam DataWidth = cva6_config_pkg::CVA6ConfigAxiDataWidth; localparam StrbWidth = DataWidth / 8; typedef logic [IdWidth-1:0] id_t; diff --git a/corev_apu/tb/ariane_tb.sv b/corev_apu/tb/ariane_tb.sv index cb75615a6..23b515c67 100644 --- a/corev_apu/tb/ariane_tb.sv +++ b/corev_apu/tb/ariane_tb.sv @@ -30,8 +30,12 @@ module ariane_tb; // cva6 configuration localparam ariane_pkg::cva6_cfg_t CVA6Cfg = { - int'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - int'(cva6_config_pkg::CVA6ConfigRvfiTrace) // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(cva6_config_pkg::CVA6ConfigRvfiTrace), // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // AxiUserWidth }; localparam type rvfi_instr_t = struct packed { logic [ariane_pkg::NRET-1:0] valid; diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index b90c952f9..bd74ac1e2 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -17,8 +17,12 @@ module ariane_testharness #( parameter ariane_pkg::cva6_cfg_t CVA6Cfg = { - int'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts - int'(cva6_config_pkg::CVA6ConfigRvfiTrace) // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigNrCommitPorts), // NrCommitPorts + unsigned'(cva6_config_pkg::CVA6ConfigRvfiTrace), // IsRVFI + unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth), // AxiAddrWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth), // AxiDataWidth + unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth), // AxiIdWidth + unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth) // AxiUserWidth }, parameter type rvfi_instr_t = struct packed { logic [ariane_pkg::NRET-1:0] valid; @@ -314,17 +318,15 @@ module ariane_testharness #( `AXI_ASSIGN_TO_RESP(dm_axi_m_resp, slave[1]) axi_adapter #( + .CVA6Cfg ( CVA6Cfg ), .DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ADDR_WIDTH ( ariane_axi_soc::AddrWidth ), - .AXI_DATA_WIDTH ( ariane_axi_soc::DataWidth ), - .AXI_ID_WIDTH ( ariane_soc::IdWidth ), .axi_req_t ( ariane_axi::req_t ), .axi_rsp_t ( ariane_axi::resp_t ) ) i_dm_axi_master ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .req_i ( dm_master_req ), - .type_i ( ariane_axi::SINGLE_REQ ), + .type_i ( ariane_pkg::SINGLE_REQ ), .amo_i ( ariane_pkg::AMO_NONE ), .gnt_o ( dm_master_gnt ), .addr_i ( dm_master_add ), @@ -639,7 +641,9 @@ module ariane_testharness #( ariane #( .CVA6Cfg ( CVA6Cfg ), .rvfi_instr_t ( rvfi_instr_t ), - .ArianeCfg ( ariane_soc::ArianeSocCfg ) + .ArianeCfg ( ariane_soc::ArianeSocCfg ), + .noc_req_t ( ariane_axi::req_t ), + .noc_resp_t ( ariane_axi::resp_t ) ) i_ariane ( .clk_i ( clk_i ), .rst_ni ( ndmreset_n ), @@ -655,8 +659,8 @@ module ariane_testharness #( `else .debug_req_i ( debug_req_core ), `endif - .axi_req_o ( axi_ariane_req ), - .axi_resp_i ( axi_ariane_resp ) + .noc_req_o ( axi_ariane_req ), + .noc_resp_i ( axi_ariane_resp ) ); `AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req) diff --git a/core/include/axi_intf.sv b/corev_apu/tb/axi_intf.sv similarity index 100% rename from core/include/axi_intf.sv rename to corev_apu/tb/axi_intf.sv