diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 37fd5f60b..202ac0f82 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -49,6 +49,13 @@ asm-quest:
     - make -j${NUM_JOBS} run-asm-tests batch-mode=1
   dependencies:
     - build
+
+amo-quest:
+  stage: test_std
+  script:
+    - make -j${NUM_JOBS} run-amo-tests batch-mode=1
+  dependencies:
+    - build
     
 bench-quest:
   stage: test_std
@@ -73,6 +80,14 @@ asm2-ver:
   dependencies:
     - build    
 
+# atomics
+amo-ver:
+  stage: test_std
+  script:
+    - make -j${NUM_JOBS} run-amo-verilator 
+  dependencies:
+    - build    
+
 bench-ver:
   stage: test_std
   script:
diff --git a/.travis.yml b/.travis.yml
index c51dd518e..2a3a694de 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -88,6 +88,12 @@ jobs:
       script:
         - ci/build-riscv-tests.sh
         - make -j${NUM_JOBS} run-asm-tests2-verilator 
+    # amo tests
+    - stage: test
+      name: run amo tests
+      script:
+        - ci/build-riscv-tests.sh
+        - make -j${NUM_JOBS} run-amo-verilator 
     - stage: test
       name: run torture
       script:
diff --git a/Makefile b/Makefile
index 002c6b706..e951b4ff1 100755
--- a/Makefile
+++ b/Makefile
@@ -82,12 +82,13 @@ root-dir := $(shell pwd)
 tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
 # RISCV asm tests and benchmark setup (used for CI)
 # there is a definesd test-list with selected CI tests
-riscv-test-dir        := tmp/riscv-tests/build/isa/
-riscv-benchmarks-dir  := tmp/riscv-tests/build/benchmarks/
-riscv-asm-tests-list  := ci/riscv-asm-tests.list
-riscv-benchmarks-list := ci/riscv-benchmarks.list
-riscv-asm-tests       := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list)  | cut -b 1-)
-riscv-benchmarks      := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
+riscv-test-dir            := tmp/riscv-tests/build/isa/
+riscv-benchmarks-dir      := tmp/riscv-tests/build/benchmarks/
+riscv-asm-tests-list      := ci/riscv-asm-tests.list
+riscv-amo-tests-list  := ci/riscv-amo-tests.list
+riscv-benchmarks-list     := ci/riscv-benchmarks.list
+riscv-asm-tests           := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list)  | cut -b 1-)
+riscv-benchmarks          := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
 
 # Search here for include files (e.g.: non-standalone components)
 incdir :=
@@ -160,9 +161,15 @@ $(riscv-benchmarks): build
 run-asm-tests: $(riscv-asm-tests)
 	make check-asm-tests
 
+run-amo-tests: $(riscv-amo-tests)
+	make check-amo-tests
+
 check-asm-tests:
 	ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
 
+check-amo-tests:
+	ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
+
 # can use -jX to run ci tests in parallel using X processes
 run-benchmarks: $(riscv-benchmarks)
 	make check-benchmarks
@@ -202,13 +209,15 @@ verilate:
 $(addsuffix -verilator,$(riscv-asm-tests)): verilate
 	$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
 
-run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
+run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests))
 
 # split into two halfs for travis jobs (otherwise they will time out)
 run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests)))
 
 run-asm-tests2-verilator: $(addsuffix -verilator, $(filter-out rv64ui-v-% ,$(riscv-asm-tests)))
 
+run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
+
 
 $(addsuffix -verilator,$(riscv-benchmarks)): verilate
 	$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
diff --git a/ci/check-tests.sh b/ci/check-tests.sh
index e7b6e52a8..2325d7f6d 100755
--- a/ci/check-tests.sh
+++ b/ci/check-tests.sh
@@ -2,7 +2,7 @@
 # check simulation output (only for questasim flow)
 #
 # $1 simulation output file basename
-# $2 list file containing the test names
+# $2 number of tests to check
 #
 
 ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
diff --git a/ci/riscv-asm-tests.list b/ci/riscv-asm-tests.list
index e03f7c392..3ecc8933c 100644
--- a/ci/riscv-asm-tests.list
+++ b/ci/riscv-asm-tests.list
@@ -127,41 +127,3 @@ rv64um-v-divw
 rv64um-v-divuw
 rv64um-v-remw
 rv64um-v-remuw
-rv64ua-p-amoadd_d
-rv64ua-p-amoadd_w
-rv64ua-p-amoor_d
-rv64ua-p-amoor_w
-rv64ua-p-amoand_d
-rv64ua-p-amoand_w
-rv64ua-p-amoswap_d
-rv64ua-p-amoswap_w
-rv64ua-p-amoxor_d
-rv64ua-p-amoxor_w
-rv64ua-p-amomax_d
-rv64ua-p-amomaxu_d
-rv64ua-p-amomaxu_w
-rv64ua-p-amomax_w
-rv64ua-p-amomin_d
-rv64ua-p-amomin_w
-rv64ua-p-amominu_d
-rv64ua-p-amominu_w
-rv64ua-p-lrsc
-rv64ua-v-amoadd_d
-rv64ua-v-amoadd_w
-rv64ua-v-amoor_d
-rv64ua-v-amoor_w
-rv64ua-v-amoand_d
-rv64ua-v-amoand_w
-rv64ua-v-amoswap_d
-rv64ua-v-amoswap_w
-rv64ua-v-amoxor_d
-rv64ua-v-amoxor_w
-rv64ua-v-amomax_d
-rv64ua-v-amomaxu_d
-rv64ua-v-amomaxu_w
-rv64ua-v-amomax_w
-rv64ua-v-amomin_d
-rv64ua-v-amomin_w
-rv64ua-v-amominu_d
-rv64ua-v-amominu_w
-rv64ua-v-lrsc
diff --git a/src/cache_subsystem/serpent_dcache_ctrl.sv b/src/cache_subsystem/serpent_dcache_ctrl.sv
index 1c2ecff4a..ee811afc0 100644
--- a/src/cache_subsystem/serpent_dcache_ctrl.sv
+++ b/src/cache_subsystem/serpent_dcache_ctrl.sv
@@ -141,6 +141,7 @@ module serpent_dcache_ctrl #(
                 // kill -> go back to IDLE
                 if(req_port_i.kill_req) begin
                     state_d = IDLE;
+                    req_port_o.data_rvalid = 1'b1;
                 end else if(req_port_i.tag_valid | state_q==REPLAY_READ) begin
                     save_tag = (state_q!=REPLAY_READ);
                     if(wr_cl_vld_i | ~rd_ack_q) begin
@@ -166,6 +167,7 @@ module serpent_dcache_ctrl #(
                 miss_req_o = 1'b1;
 
                 if(req_port_i.kill_req) begin
+                    req_port_o.data_rvalid = 1'b1;
                     if(miss_ack_i) begin
                         state_d = KILL_MISS;
                     end else begin    
@@ -182,6 +184,7 @@ module serpent_dcache_ctrl #(
             // returns. 
             MISS_WAIT: begin
                 if(req_port_i.kill_req) begin
+                    req_port_o.data_rvalid = 1'b1;
                     if(miss_rtrn_vld_i) begin
                         state_d = IDLE;
                     end else begin
@@ -197,6 +200,7 @@ module serpent_dcache_ctrl #(
             REPLAY_REQ: begin
                 rd_req_o = 1'b1;
                 if (req_port_i.kill_req) begin
+                    req_port_o.data_rvalid = 1'b1;
                     state_d = IDLE;
                 end else if(rd_ack_i) begin
                     state_d = REPLAY_READ;