diff --git a/src/if_stage.sv b/src/if_stage.sv index d293ce862..bf6c0d883 100644 --- a/src/if_stage.sv +++ b/src/if_stage.sv @@ -180,26 +180,26 @@ module if_stage ( begin : IF_ID_PIPE_REGISTERS if (rst_ni == 1'b0) begin - instr_valid_id_o <= 1'b0; - instr_rdata_id_o <= '0; - illegal_c_insn_id_o <= 1'b0; - is_compressed_id_o <= 1'b0; - pc_id_o <= '0; - ex_o <= '{default: 0}; + instr_valid_id_o <= 1'b0; + instr_rdata_id_o <= '0; + illegal_c_insn_id_o <= 1'b0; + is_compressed_id_o <= 1'b0; + pc_id_o <= '0; + ex_o <= '{default: 0}; end else begin if (if_valid) begin - instr_valid_id_o <= 1'b1; - instr_rdata_id_o <= instr_decompressed; - illegal_c_insn_id_o <= illegal_c_insn; - is_compressed_id_o <= instr_compressed_int; - pc_id_o <= pc_if_o; - ex_o.cause <= 64'b0; // TODO: Output exception - ex_o.tval <= 64'b0; // TODO: Output exception - ex_o.valid <= 1'b0; // TODO: Output exception + instr_valid_id_o <= 1'b1; + instr_rdata_id_o <= instr_decompressed; + illegal_c_insn_id_o <= illegal_c_insn; + is_compressed_id_o <= instr_compressed_int; + pc_id_o <= pc_if_o; + ex_o.cause <= 64'b0; // TODO: Output exception + ex_o.tval <= 64'b0; // TODO: Output exception + ex_o.valid <= 1'b0; // TODO: Output exception end else if (clear_instr_valid_i) begin instr_valid_id_o <= 1'b0; end diff --git a/tb/agents/core_if/core_if.sv b/tb/agents/core_if/core_if.sv new file mode 100755 index 000000000..6e74292d3 --- /dev/null +++ b/tb/agents/core_if/core_if.sv @@ -0,0 +1,49 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 8.5.2017 +// Description: Core Interface +// +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. +// +`ifndef CORE_IF_SV +`define CORE_IF_SV +interface core_if ( + input clk + ); + + wire clock_en; + wire test_en; + wire fetch_enable; + wire core_busy; + wire [63:0] boot_addr; + wire [3:0] core_id; + wire [5:0] cluster_id; + wire irq; + wire [4:0] irq_id; + wire irq_ack; + wire irq_sec; + wire sec_lvl; + + clocking mck @(posedge clk); + output clock_en, test_en, fetch_enable, boot_addr, core_id, cluster_id, irq, irq_id, irq_sec; + input core_busy, sec_lvl, irq_ack; + endclocking + + clocking pck @(posedge clk); + input clock_en, test_en, fetch_enable, boot_addr, core_id, cluster_id, irq, irq_id, irq_sec, core_busy, sec_lvl, irq_ack; + endclocking + +endinterface +`endif \ No newline at end of file diff --git a/tb/agents/core_if/core_if_agent.svh b/tb/agents/core_if/core_if_agent.svh new file mode 100644 index 000000000..e86733e9f --- /dev/null +++ b/tb/agents/core_if/core_if_agent.svh @@ -0,0 +1,57 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: Main agent object core_if. Builds and instantiates the appropriate +// subcomponents like the monitor, driver etc. all based on the +// agent configuration object. +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_agent extends uvm_component; + // UVM Factory Registration Macro + `uvm_component_utils(core_if_agent) + //------------------------------------------ + // Data Members + //------------------------------------------ + core_if_agent_config m_cfg; + //------------------------------------------ + // Component Members + //------------------------------------------ + uvm_analysis_port #(core_if_seq_item) ap; + core_if_driver m_driver; + core_if_monitor m_monitor; + core_if_sequencer m_sequencer; + //------------------------------------------ + // Methods + //------------------------------------------ + // Standard UVM Methods: + function new(string name = "core_if_agent", uvm_component parent = null); + super.new(name, parent); + endfunction : new + + function void build_phase(uvm_phase phase); + if (!uvm_config_db #(core_if_agent_config)::get(this, "", "core_if_agent_config", m_cfg) ) + `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration core_if_agent_config from uvm_config_db. Have you set() it?") + + m_driver = core_if_driver::type_id::create("m_driver", this); + m_sequencer = core_if_sequencer::type_id::create("m_sequencer", this); + m_monitor = core_if_monitor::type_id::create("m_monitor", this); + endfunction : build_phase + + function void connect_phase(uvm_phase phase); + + m_driver.seq_item_port.connect(m_sequencer.seq_item_export); + // m_monitor.ap.connect(m_cov_monitor.analysis_port) + m_driver.m_cfg = m_cfg; + m_monitor.m_cfg = m_cfg; + + endfunction: connect_phase +endclass : core_if_agent diff --git a/tb/agents/core_if/core_if_agent_config.svh b/tb/agents/core_if/core_if_agent_config.svh new file mode 100644 index 000000000..5cb31617f --- /dev/null +++ b/tb/agents/core_if/core_if_agent_config.svh @@ -0,0 +1,37 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: Agent configuration object core_if +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_agent_config extends uvm_object; + + // UVM Factory Registration Macro + `uvm_object_utils(core_if_agent_config) + + // Virtual Interface + virtual core_if m_vif; + //------------------------------------------ + // Data Members + //------------------------------------------ + // Is the agent active or passive + uvm_active_passive_enum active = UVM_ACTIVE; + + // Standard UVM Methods: + function new(string name = "core_if_agent_config"); + super.new(name); + endfunction : new + +endclass : core_if_agent_config + + + diff --git a/tb/agents/core_if/core_if_agent_pkg.sv b/tb/agents/core_if/core_if_agent_pkg.sv new file mode 100644 index 000000000..6cc6b0d49 --- /dev/null +++ b/tb/agents/core_if/core_if_agent_pkg.sv @@ -0,0 +1,37 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core_if_agent package - compile unit +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +package core_if_agent_pkg; + // UVM Import + import uvm_pkg::*; + `include "uvm_macros.svh" + + // Sequence item to model transactions + `include "core_if_seq_item.svh" + // Agent configuration object + `include "core_if_agent_config.svh" + // Driver + `include "core_if_driver.svh" + // Coverage monitor + // `include "core_if_coverage_monitor.svh" + // Monitor that includes analysis port + `include "core_if_monitor.svh" + // Sequencer + `include "core_if_sequencer.svh" + // Main agent + `include "core_if_agent.svh" + // Sequence + `include "core_if_sequence.svh" +endpackage: core_if_agent_pkg \ No newline at end of file diff --git a/tb/agents/core_if/core_if_driver.svh b/tb/agents/core_if/core_if_driver.svh new file mode 100644 index 000000000..a5bf57625 --- /dev/null +++ b/tb/agents/core_if/core_if_driver.svh @@ -0,0 +1,58 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: Driver for interface core_if +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_driver extends uvm_driver #(core_if_seq_item); + + // UVM Factory Registration Macro + `uvm_component_utils(core_if_driver) + + // Virtual Interface + virtual core_if m_vif; + + //--------------------- + // Data Members + //--------------------- + core_if_agent_config m_cfg; + + // Standard UVM Methods: + function new(string name = "core_if_driver", uvm_component parent = null); + super.new(name, parent); + endfunction + + task run_phase(uvm_phase phase); + // core_if_seq_item cmd; + // seq_item_port.get_next_item(cmd); + + // seq_item_port.item_done(); + m_vif.mck.test_en <= 1'b0; + m_vif.mck.boot_addr <= 64'b0; + m_vif.mck.core_id <= 4'b0; + m_vif.mck.cluster_id <= 6'b0; + m_vif.mck.irq <= 1'b0; + m_vif.mck.irq_id <= 5'b0; + m_vif.mck.irq_sec <= 1'b0; + m_vif.mck.fetch_enable <= 1'b0; + + repeat (20) @(m_vif.mck); + m_vif.mck.fetch_enable <= 1'b1; + endtask : run_phase + + function void build_phase(uvm_phase phase); + if (!uvm_config_db #(core_if_agent_config)::get(this, "", "core_if_agent_config", m_cfg) ) + `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration core_if_agent_config from uvm_config_db. Have you set() it?") + + m_vif = m_cfg.m_vif; + endfunction: build_phase +endclass : core_if_driver diff --git a/tb/agents/core_if/core_if_monitor.svh b/tb/agents/core_if/core_if_monitor.svh new file mode 100644 index 000000000..662067cdd --- /dev/null +++ b/tb/agents/core_if/core_if_monitor.svh @@ -0,0 +1,62 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core_if Monitor, monitors the DUT's pins and writes out +// appropriate sequence items as defined for this particular dut +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_monitor extends uvm_component; + + // UVM Factory Registration Macro + `uvm_component_utils(core_if_monitor) + + // analysis port + uvm_analysis_port #(core_if_seq_item) m_ap; + + // Virtual Interface + virtual core_if m_vif; + + //--------------------- + // Data Members + //--------------------- + core_if_agent_config m_cfg; + + // Standard UVM Methods: + function new(string name = "core_if_driver", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + if (!uvm_config_db #(core_if_agent_config)::get(this, "", "core_if_agent_config", m_cfg) ) + `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration core_if_agent_config from uvm_config_db. Have you set() it?") + + m_ap = new("m_ap", this); + + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + // connect virtual interface + m_vif = m_cfg.m_vif; + endfunction + + task run_phase(uvm_phase phase); + + core_if_seq_item cmd = core_if_seq_item::type_id::create("cmd"); + core_if_seq_item cloned_item; + + + $cast(cloned_item, cmd.clone()); + m_ap.write(cloned_item); + + endtask : run_phase +endclass : core_if_monitor diff --git a/tb/agents/core_if/core_if_seq_item.svh b/tb/agents/core_if/core_if_seq_item.svh new file mode 100644 index 000000000..2d5c4143a --- /dev/null +++ b/tb/agents/core_if/core_if_seq_item.svh @@ -0,0 +1,89 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core_if Sequence item +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_seq_item extends uvm_sequence_item; + + // UVM Factory Registration Macro + `uvm_object_utils(core_if_seq_item) + + //------------------------------------------ + // Data Members (Outputs rand, inputs non-rand) + //------------------------------------------ + // TODO: set data members + + //------------------------------------------ + // Methods + //------------------------------------------ + + // Standard UVM Methods: + function new(string name = "core_if_seq_item"); + super.new(name); + endfunction + + function void do_copy(uvm_object rhs); + core_if_seq_item rhs_; + + if(!$cast(rhs_, rhs)) begin + `uvm_fatal("do_copy", "cast of rhs object failed") + end + super.do_copy(rhs); + // Copy over data members: + // e.g.: + // operator = rhs_.operator; + + endfunction:do_copy + + function bit do_compare(uvm_object rhs, uvm_comparer comparer); + core_if_seq_item rhs_; + + if(!$cast(rhs_, rhs)) begin + `uvm_error("do_copy", "cast of rhs object failed") + return 0; + end + // TODO + return super.do_compare(rhs, comparer); // && operator == rhs_.operator + + endfunction:do_compare + + function string convert2string(); + string s; + + $sformat(s, "%s\n", super.convert2string()); + // Convert to string function reusing s: + // TODO + // $sformat(s, "%s\n operator\n", s, operator); + return s; + + endfunction:convert2string + + function void do_print(uvm_printer printer); + if(printer.knobs.sprint == 0) begin + $display(convert2string()); + end + else begin + printer.m_string = convert2string(); + end + endfunction:do_print + + function void do_record(uvm_recorder recorder); + super.do_record(recorder); + + // Use the record macros to record the item fields: + // TODO + // `uvm_record_field("operator", operator) + endfunction:do_record + +endclass : core_if_seq_item diff --git a/tb/agents/core_if/core_if_sequence.svh b/tb/agents/core_if/core_if_sequence.svh new file mode 100644 index 000000000..34621e675 --- /dev/null +++ b/tb/agents/core_if/core_if_sequence.svh @@ -0,0 +1,53 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core_if sequence consisting of core_if_sequence_items +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_sequence extends uvm_sequence #(core_if_seq_item); + + // UVM Factory Registration Macro + `uvm_object_utils(core_if_sequence) + + //----------------------------------------------- + // Data Members (Outputs rand, inputs non-rand) + //----------------------------------------------- + + + //------------------------------------------ + // Constraints + //------------------------------------------ + + + + //------------------------------------------ + // Methods + //------------------------------------------ + + // Standard UVM Methods: + function new(string name = "core_if_sequence"); + super.new(name); + endfunction + + task body; + core_if_seq_item req; + + begin + req = core_if_seq_item::type_id::create("req"); + start_item(req); + assert(req.randomize()); + finish_item(req); + end + endtask:body + +endclass : core_if_sequence \ No newline at end of file diff --git a/tb/agents/core_if/core_if_sequencer.svh b/tb/agents/core_if/core_if_sequencer.svh new file mode 100644 index 000000000..6cc1129b4 --- /dev/null +++ b/tb/agents/core_if/core_if_sequencer.svh @@ -0,0 +1,29 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core_if Sequencer for core_if_sequence_item +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_if_sequencer extends uvm_sequencer #(core_if_seq_item); + + // UVM Factory Registration Macro + `uvm_component_utils(core_if_sequencer) + + // Standard UVM Methods: + function new(string name="core_if_sequencer", uvm_component parent = null); + super.new(name, parent); + endfunction + +endclass: core_if_sequencer + + diff --git a/tb/core_tb.sv b/tb/core_tb.sv index 41b6af5a5..06043b05f 100644 --- a/tb/core_tb.sv +++ b/tb/core_tb.sv @@ -10,77 +10,61 @@ import ariane_pkg::*; module core_tb; + import uvm_pkg::*; + import core_lib_pkg::*; logic clk_i; logic rst_ni; - logic clock_en_i; - logic test_en_i; - logic fetch_enable_i; - logic core_busy_o; - logic [63:0] boot_addr_i; - logic [3:0] core_id_i; - logic [5:0] cluster_id_i; + mem_if #(.DATA_WIDTH(32)) instr_if(clk_i); mem_if data_if(clk_i); - logic irq_i; - logic [4:0] irq_id_i; - logic irq_ack_o; - logic irq_sec_i; - logic sec_lvl_o; debug_if debug_if(); - - assign test_en_i = 1'b0; - assign boot_addr_i = 64'b0; - assign core_id_i = 4'b0; - assign cluster_id_i = 6'b0; - assign irq_i = 1'b0; - assign irq_id_i = 5'b0; - assign irq_sec_i = 1'b0; + core_if core_if(clk_i); ariane dut ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clock_en_i ( clock_en_i ), - .test_en_i ( test_en_i ), - .fetch_enable_i ( fetch_enable_i ), - .core_busy_o ( core_busy_o ), - .ext_perf_counters_i ( ), - .boot_addr_i ( boot_addr_i ), - .core_id_i ( core_id_i ), - .cluster_id_i ( cluster_id_i ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clock_en_i ( core_if.clock_en ), + .test_en_i ( core_if.test_en ), + .fetch_enable_i ( core_if.fetch_enable ), + .core_busy_o ( core_if.core_busy ), + .ext_perf_counters_i ( ), + .boot_addr_i ( core_if.boot_addr ), + .core_id_i ( core_if.core_id ), + .cluster_id_i ( core_if.cluster_id ), .instr_if_address_o ( instr_if.address ), - .instr_if_data_req_o ( instr_if.data_req ), + .instr_if_data_req_o ( instr_if.data_req & instr_if.data_req ), .instr_if_data_be_o ( instr_if.data_be ), .instr_if_data_gnt_i ( instr_if.data_gnt ), .instr_if_data_rvalid_i ( instr_if.data_rvalid ), .instr_if_data_rdata_i ( instr_if.data_rdata ), - .data_if_address_o ( data_if.address ), - .data_if_data_wdata_o ( data_if.data_wdata ), - .data_if_data_req_o ( data_if.data_req ), - .data_if_data_we_o ( data_if.data_we ), - .data_if_data_be_o ( data_if.data_be ), - .data_if_data_gnt_i ( data_if.data_gnt ), - .data_if_data_rvalid_i ( data_if.data_rvalid ), - .data_if_data_rdata_i ( data_if.data_rdata ), + .data_if_address_o ( data_if.address ), + .data_if_data_wdata_o ( data_if.data_wdata ), + .data_if_data_req_o ( data_if.data_req ), + .data_if_data_we_o ( data_if.data_we ), + .data_if_data_be_o ( data_if.data_be ), + .data_if_data_gnt_i ( data_if.data_gnt ), + .data_if_data_rvalid_i ( data_if.data_rvalid ), + .data_if_data_rdata_i ( data_if.data_rdata ), - .irq_i ( irq_i ), - .irq_id_i ( irq_id_i ), - .irq_ack_o ( irq_ack_o ), - .irq_sec_i ( irq_sec_i ), - .sec_lvl_o ( sec_lvl_o ), + .irq_i ( core_if.irq ), + .irq_id_i ( core_if.irq_id ), + .irq_ack_o ( core_if.irq_ack ), + .irq_sec_i ( core_if.irq_sec ), + .sec_lvl_o ( core_if.sec_lvl ), - .debug_req_i ( ), - .debug_gnt_o ( ), - .debug_rvalid_o ( ), - .debug_addr_i ( ), - .debug_we_i ( ), - .debug_wdata_i ( ), - .debug_rdata_o ( ), - .debug_halted_o ( ), - .debug_halt_i ( ), - .debug_resume_i ( ) + .debug_req_i ( ), + .debug_gnt_o ( ), + .debug_rvalid_o ( ), + .debug_addr_i ( ), + .debug_we_i ( ), + .debug_wdata_i ( ), + .debug_rdata_o ( ), + .debug_halted_o ( ), + .debug_halt_i ( ), + .debug_resume_i ( ) ); // clock process @@ -94,64 +78,58 @@ module core_tb; #10ns clk_i = ~clk_i; end - initial begin - fetch_enable_i = 1'b0; - wait(rst_ni) - #80ns fetch_enable_i = 1'b1; - - end - - assign instr_if.data_gnt = instr_if.data_req; - - program testbench (mem_if instr_if); - logic [7:0] imem [400]; - logic [63:0] address [$]; - logic [63:0] addr; - // instruction memory + program testbench (core_if core_if, mem_if instr_if); initial begin - // read mem file - $readmemh("add_test.v", imem, 64'b0); - $display("Read instruction memory file"); - instr_if.mck.data_rdata <= 32'b0; - // apply stimuli for instruction interface - forever begin - // instr_if.mck.data_rvalid <= 1'b0; - // instr_if.mck.data_gnt <= 1'b0; - - @(instr_if.mck) - instr_if.mck.data_rvalid <= 1'b0; - fork - imem_read: begin - // instr_if.mck.data_rvalid <= 1'b0; - if (instr_if.data_req) begin - address.push_back(instr_if.mck.address); - end - end - - imem_write: begin - if (address.size() != 0) begin - instr_if.mck.data_rvalid <= 1'b1; - addr = address.pop_front(); - instr_if.mck.data_rdata <= { - imem[$unsigned(addr + 3)], - imem[$unsigned(addr + 2)], - imem[$unsigned(addr + 1)], - imem[$unsigned(addr + 0)] - }; - $display("Address: %0h, Data: %0h", addr, { - imem[$unsigned(addr + 3)], - imem[$unsigned(addr + 2)], - imem[$unsigned(addr + 1)], - imem[$unsigned(addr + 0)] - }); - end else - instr_if.mck.data_rvalid <= 1'b0; - end - join_none - - end + uvm_config_db #(virtual core_if)::set(null, "uvm_test_top", "core_if", core_if); end + // logic [7:0] imem [400]; + // logic [63:0] address [$]; + // logic [63:0] addr; + // // instruction memory + // initial begin + // // read mem file + // $readmemh("add_test.v", imem, 64'b0); + // $display("Read instruction memory file"); + // instr_if.mck.data_rdata <= 32'b0; + // // apply stimuli for instruction interface + // forever begin + // // instr_if.mck.data_rvalid <= 1'b0; + // // instr_if.mck.data_gnt <= 1'b0; + + // @(instr_if.mck) + // instr_if.mck.data_rvalid <= 1'b0; + // fork + // imem_read: begin + // // instr_if.mck.data_rvalid <= 1'b0; + // if (instr_if.data_req) begin + // address.push_back(instr_if.mck.address); + // end + // end + + // imem_write: begin + // if (address.size() != 0) begin + // instr_if.mck.data_rvalid <= 1'b1; + // addr = address.pop_front(); + // instr_if.mck.data_rdata <= { + // imem[$unsigned(addr + 3)], + // imem[$unsigned(addr + 2)], + // imem[$unsigned(addr + 1)], + // imem[$unsigned(addr + 0)] + // }; + // $display("Address: %0h, Data: %0h", addr, { + // imem[$unsigned(addr + 3)], + // imem[$unsigned(addr + 2)], + // imem[$unsigned(addr + 1)], + // imem[$unsigned(addr + 0)] + // }); + // end else + // instr_if.mck.data_rvalid <= 1'b0; + // end + // join_none + + // end + // end endprogram - testbench tb(instr_if); + testbench tb(core_if, instr_if); endmodule \ No newline at end of file diff --git a/tb/env/core/core_env.svh b/tb/env/core/core_env.svh new file mode 100644 index 000000000..247feb07c --- /dev/null +++ b/tb/env/core/core_env.svh @@ -0,0 +1,56 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: Environment which instantiates the agent and all environment +// related components such as a scoreboard etc. +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_env extends uvm_env; + + // UVM Factory Registration Macro + `uvm_component_utils(core_env) + + //------------------------------------------ + // Data Members + //------------------------------------------ + core_if_agent m_core_if_agent; + core_if_sequencer m_core_if_sequencer; + core_env_config m_cfg; + //------------------------------------------ + // Methods + //------------------------------------------ + + // Standard UVM Methods: + function new(string name = "core_env", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + if (!uvm_config_db #(core_env_config)::get(this, "", "core_env_config", m_cfg)) + `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration core_env_config from uvm_config_db. Have you set() it?") + // Conditional instantiation goes here + + // Create agent configuration + uvm_config_db #(core_if_agent_config)::set(this, "m_core_if_agent*", + "core_if_agent_config", + m_cfg.m_core_if_agent_config); + m_core_if_agent = core_if_agent::type_id::create("m_core_if_agent", this); + + // Get sequencer + m_core_if_sequencer = core_if_sequencer::type_id::create("m_core_if_sequencer", this); + + endfunction:build_phase + + function void connect_phase(uvm_phase phase); + m_core_if_sequencer = m_core_if_agent.m_sequencer; + endfunction: connect_phase +endclass : core_env diff --git a/tb/env/core/core_env_config.svh b/tb/env/core/core_env_config.svh new file mode 100644 index 000000000..20b45f8e7 --- /dev/null +++ b/tb/env/core/core_env_config.svh @@ -0,0 +1,29 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core configuration object +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_env_config extends uvm_object; + + // UVM Factory Registration Macro + `uvm_object_utils(core_env_config) + + // a functional unit master interface + virtual core_if m_core_if; + + // an agent config + + core_if_agent_config m_core_if_agent_config; + +endclass : core_env_config diff --git a/tb/env/core/core_env_pkg.sv b/tb/env/core/core_env_pkg.sv new file mode 100644 index 000000000..245231163 --- /dev/null +++ b/tb/env/core/core_env_pkg.sv @@ -0,0 +1,26 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core package +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +package core_env_pkg; + // Standard UVM import & include: + import uvm_pkg::*; + `include "uvm_macros.svh" + // Testbench related imports + import core_if_agent_pkg::*; + // Includes for the config for the environment + `include "core_env_config.svh" + // Includes the environment + `include "core_env.svh" +endpackage diff --git a/tb/test/core/core_lib_pkg.sv b/tb/test/core/core_lib_pkg.sv new file mode 100644 index 000000000..c44e906df --- /dev/null +++ b/tb/test/core/core_lib_pkg.sv @@ -0,0 +1,41 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: Main test package contains all necessary packages +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +package core_lib_pkg; + // Standard UVM import & include: + import uvm_pkg::*; + `include "uvm_macros.svh" + // Import the memory interface agent + import core_if_agent_pkg::*; + // ------------------------------------------------ + // Environment which will be instantiated + // ------------------------------------------------ + import core_env_pkg::*; + // ---------------- + // Sequence Package + // ---------------- + import core_sequence_pkg::*; + // Test based includes like base test class and specializations of it + // ---------------- + // Base test class + // ---------------- + `include "core_test_base.svh" + // ------------------- + // Child test classes + // ------------------- + `include "core_test.svh" + +endpackage diff --git a/tb/test/core/core_sequence_pkg.sv b/tb/test/core/core_sequence_pkg.sv new file mode 100644 index 000000000..548232b68 --- /dev/null +++ b/tb/test/core/core_sequence_pkg.sv @@ -0,0 +1,25 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core sequence package +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +package core_sequence_pkg; + + import core_if_agent_pkg::*; + import uvm_pkg::*; + + `include "uvm_macros.svh" + // Include your sequences here e.g.: + // `include "fibonacci_sequence.svh" +endpackage diff --git a/tb/test/core/core_test.svh b/tb/test/core/core_test.svh new file mode 100644 index 000000000..3d078cda6 --- /dev/null +++ b/tb/test/core/core_test.svh @@ -0,0 +1,50 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core main test class +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_test extends core_test_base; + // UVM Factory Registration Macro + `uvm_component_utils(core_test) + // TODO: declare sequence here + // core_sequence core; + //------------------------------------------ + // Methods + //------------------------------------------ + + // Standard UVM Methods: + function new(string name = "core_test", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + phase.raise_objection(this, "core_test"); + //fibonacci_sequence fibonacci; + super.run_phase(phase); + + // core = new("core"); + // TODO: Start sequence here + // core.start(sequencer_h); + // Testlogic goes here + #100ns; + + phase.drop_objection(this, "core_test"); + endtask + + +endclass : core_test diff --git a/tb/test/core/core_test_base.svh b/tb/test/core/core_test_base.svh new file mode 100644 index 000000000..fbea61d46 --- /dev/null +++ b/tb/test/core/core_test_base.svh @@ -0,0 +1,82 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: core base test class +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +class core_test_base extends uvm_test; + + // UVM Factory Registration Macro + `uvm_component_utils(core_test_base) + + //------------------------------------------ + // Data Members + //------------------------------------------ + + //------------------------------------------ + // Component Members + //------------------------------------------ + // environment configuration + core_env_config m_env_cfg; + // environment + core_env m_env; + core_if_sequencer sequencer_h; + + // reset_sequence reset; + // --------------------- + // Agent configuration + // --------------------- + // functional unit interface + core_if_agent_config m_core_if_cfg; + + //------------------------------------------ + // Methods + //------------------------------------------ + // standard UVM methods: + function new(string name = "core_test_base", uvm_component parent = null); + super.new(name, parent); + endfunction + + // build the environment, get all configurations + // use the factory pattern in order to facilitate UVM functionality + function void build_phase(uvm_phase phase); + // create environment + m_env_cfg = core_env_config::type_id::create("m_env_cfg"); + + // create agent configurations and assign interfaces + // create agent core_if configuration + m_core_if_cfg = core_if_agent_config::type_id::create("m_core_if_cfg"); + m_env_cfg.m_core_if_agent_config = m_core_if_cfg; + // get core_if virtual interfaces + // get master interface DB + if (!uvm_config_db #(virtual core_if)::get(this, "", "core_if", m_core_if_cfg.m_vif)) + `uvm_fatal("VIF CONFIG", "Cannot get() interface core_if from uvm_config_db. Have you set() it?") + m_env_cfg.m_core_if = m_core_if_cfg.m_vif; + + + // create environment + uvm_config_db #(core_env_config)::set(this, "*", "core_env_config", m_env_cfg); + m_env = core_env::type_id::create("m_env", this); + + endfunction + + function void end_of_elaboration_phase(uvm_phase phase); + sequencer_h = m_env.m_core_if_sequencer; + endfunction + + task run_phase(uvm_phase phase); + // reset = new("reset"); + // reset.start(sequencer_h); + endtask + +endclass : core_test_base \ No newline at end of file