diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 7ad2208f3..92e68b182 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -275,6 +275,7 @@ asic-synthesis:
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
     - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
+    - git -C ${SYNTH_SCRIPT_PATH} checkout 1e166766d2c91ca905577cccc70813a2a8bbefc2
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@@ -544,8 +545,8 @@ simu-gate:
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b testelf
-    - git -C ${SYNTH_SCRIPT_PATH} checkout cb92f846
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
+    - git -C ${SYNTH_SCRIPT_PATH} checkout 1e166766d2c91ca905577cccc70813a2a8bbefc2
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh
diff --git a/core/Flist.cva6_gate b/core/Flist.cva6_gate
index ecc3f0b40..a6e76e48f 100644
--- a/core/Flist.cva6_gate
+++ b/core/Flist.cva6_gate
@@ -62,7 +62,7 @@ ${CVA6_REPO_DIR}/pd/synth/cva6_${TARGET_CFG}_synth.v
 # Dedicated to black box in caches, cv32a65x only
 ${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv
 ${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv 
-${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_1rw_00000006_0000001a_00000040.sv
+${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv
 
 ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
 ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper_cache_techno.sv
diff --git a/pd/synth/Makefile b/pd/synth/Makefile
index c56c6e428..483912214 100644
--- a/pd/synth/Makefile
+++ b/pd/synth/Makefile
@@ -60,7 +60,7 @@ rm_synth: pre_cva6_synth
 	cp Flist.cva6_synth ../../$(SYNTH_FLOW_NAME)/synth/
 	CVA6_REPO_DIR=$(CVA6_REPO_DIR) make -C ../../$(SYNTH_FLOW_NAME)/synth/ platform_synth_topo
 	sed -i -n -e '/module hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
-	sed -i -n -e '/module hpdcache_sram_1rw_00000006_0000001a_00000040/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
+	sed -i -n -e '/module hpdcache_sram_1rw_00000006_0000001c_00000040/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
 	echo $(NAND2_AREA) > $(DESIGN_NAME)_$(TARGET)/nand2area.txt
 
 cva6_read:
diff --git a/pd/synth/hpdcache_sram_1rw_00000006_0000001a_00000040.sv b/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv
similarity index 91%
rename from pd/synth/hpdcache_sram_1rw_00000006_0000001a_00000040.sv
rename to pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv
index 138cfdea5..f933dc663 100644
--- a/pd/synth/hpdcache_sram_1rw_00000006_0000001a_00000040.sv
+++ b/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv
@@ -23,10 +23,10 @@
  *  Description   : SRAM behavioral model
  *  History       :
  */
-module hpdcache_sram_1rw_00000006_0000001a_00000040
+module hpdcache_sram_1rw_00000006_0000001c_00000040
 #(
     parameter int unsigned ADDR_SIZE = 6,
-    parameter int unsigned DATA_SIZE = 26,
+    parameter int unsigned DATA_SIZE = 28,
     parameter int unsigned DEPTH = 2**ADDR_SIZE
 )
 (
@@ -57,4 +57,4 @@ module hpdcache_sram_1rw_00000006_0000001a_00000040
             rdata <= mem[addr];
         end
     end : mem_update_ff
-endmodule : hpdcache_sram_1rw_00000006_0000001a_00000040
+endmodule : hpdcache_sram_1rw_00000006_0000001c_00000040