diff --git a/src/ariane.sv b/src/ariane.sv
index f75709ee8..37f295967 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -497,6 +497,7 @@ module ariane
     assign tracer_if.commit_instr      = commit_instr_id_commit;
     assign tracer_if.commit_ack        = commit_ack;
     // address translation
+    // assign tracer_if.vaddress_valid    = ex_stage_i.lsu_i.mmu_i.lsu_valid_o
     assign tracer_if.translation_valid = ex_stage_i.lsu_i.mmu_i.lsu_valid_o;
     assign tracer_if.vaddr             = ex_stage_i.lsu_i.mmu_i.lsu_vaddr_i;
     assign tracer_if.paddr             = ex_stage_i.lsu_i.mmu_i.lsu_paddr_o;
diff --git a/src/load_unit.sv b/src/load_unit.sv
index 15f2aa692..c71be0c15 100644
--- a/src/load_unit.sv
+++ b/src/load_unit.sv
@@ -146,7 +146,7 @@ module load_unit (
 
                 // we make a new request as soon as the page offset does not match anymore
                 if (!page_offset_matches_i) begin
-                    NS = IDLE;
+                    NS = WAIT_GNT;
                 end
             end
 
diff --git a/src/lsu.sv b/src/lsu.sv
index ad9637e29..21008bce9 100644
--- a/src/lsu.sv
+++ b/src/lsu.sv
@@ -488,14 +488,6 @@ module lsu #(
     always_comb begin : input_select
         // if we are stalling use the values we saved
         if (lsu_ready_o) begin
-            valid     = valid_q;
-            vaddr     = vaddr_q;
-            data      = data_q;
-            fu        = fu_q;
-            operator  = operator_q;
-            trans_id  = trans_id_q;
-            be        = be_q;
-        end else begin // otherwise bypass them
             valid     = lsu_valid_i;
             vaddr     = vaddr_i;
             data      = operand_b_i;
@@ -503,6 +495,14 @@ module lsu #(
             operator  = operator_i;
             trans_id  = trans_id_i;
             be        = be_i;
+        end else begin // otherwise bypass them
+            valid     = valid_q;
+            vaddr     = vaddr_q;
+            data      = data_q;
+            fu        = fu_q;
+            operator  = operator_q;
+            trans_id  = trans_id_q;
+            be        = be_q;
         end
     end
     // 1st register stage
diff --git a/src/mmu.sv b/src/mmu.sv
index 08c15daf8..473d5c256 100644
--- a/src/mmu.sv
+++ b/src/mmu.sv
@@ -48,10 +48,12 @@ module mmu #(
         input  logic [63:0]                     lsu_vaddr_i,      // virtual address in
         input  logic                            lsu_is_store_i,   // the translation is requested by a store
         // if we need to walk the page table we can't grant in the same cycle
+        // Cycle 0
+        output logic                            lsu_dtlb_hit_o,   // sent in the same cycle as the request if translation hits in the DTLB
+        // Cycle 1
         output logic                            lsu_valid_o,      // translation is valid
         output logic [63:0]                     lsu_paddr_o,      // translated address
         output exception                        lsu_exception_o,  // address translation threw an exception
-        output logic                            lsu_dtlb_hit_o,   // send in the same cycle as the request if translation hits in the DTLB
         // General control signals
         input priv_lvl_t                        priv_lvl_i,
         input priv_lvl_t                        ld_st_priv_lvl_i,
diff --git a/src/store_unit.sv b/src/store_unit.sv
index e5ebd7f94..679771c41 100644
--- a/src/store_unit.sv
+++ b/src/store_unit.sv
@@ -238,6 +238,10 @@ module store_unit (
         if ((vaddr_i[11:3] == st_buffer_paddr[11:3]) && st_buffer_valid) begin
             page_offset_matches_o = 1'b1;
         end
+
+        if ((vaddr_i[11:3] == paddr_i[11:3]) && (CS == VALID_STORE)) begin
+            page_offset_matches_o = 1'b1;
+        end
     end
 
 endmodule
\ No newline at end of file