diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv
index d70844700..0b051a593 100644
--- a/include/ariane_pkg.sv
+++ b/include/ariane_pkg.sv
@@ -306,18 +306,7 @@ package ariane_pkg;
     // Debug Unit
     // ----------------------
 
-    typedef struct packed {
-        logic        halt;          // core is halted
-        logic        sste;          // single step enable
-        logic        ssth;          // single step hit
-        logic        sleep;         // core is sleeping
-        logic [63:0] ie;            // enable interrupt/exception
-        logic [63:0] cause;         // cause of encountered exception or interrupt
-        logic [63:0] npc;           // next PC
-        logic [63:0] ppc;           // previous PC
-    } debug_reg_t;
-
-    typedef enmu logic [14:0] {
+    typedef enum logic [14:0] {
         DBG_CTRL     = 15'h0,
         DBG_HIT      = 15'h4,
         DBG_IE       = 15'h8,
@@ -338,6 +327,8 @@ package ariane_pkg;
         DBG_BPDATA6  = 15'h74,
         DBG_BPCTRL7  = 15'h78,
         DBG_BPDATA7  = 15'h7C,
+        DBG_GPR      = 15'h4xx,
+        DBG_CSR      = 15'h5xx,
         DBG_NPC      = 15'h2000,
         DBG_PPC      = 15'h2004
     } debug_reg_t;
diff --git a/src/debug_unit.sv b/src/debug_unit.sv
index 300e23967..6e56dfbe4 100755
--- a/src/debug_unit.sv
+++ b/src/debug_unit.sv
@@ -98,14 +98,22 @@ module debug_unit (
             // we can immediately grant the request
             debug_gnt_o = 1'b1;
             // decode debug address
-            case (debug_addr_i)
+            casex (debug_addr_i)
                 DBG_CTRL:  rdata_n = {32'b0, 15'b0, (CS == HALTED), 15'b0, (CS == SINGLE_STEP)};
-                DBG_HIT:   rdata_n = {63'b0, sshit};
+                DBG_HIT:   rdata_n = {64'b0};
                 DBG_IE:    rdata_n = dbg_ie_q;
                 DBG_CAUSE: rdata_n = dbg_cause_q;
                 DBG_NPC:   rdata_n = commit_instr_i.pc;
                 DBG_PPC:   rdata_n = ppc_q;
+                DBG_GPR: begin
+
+                end
+
+                DBG_CSR: begin
+
+                end
             endcase
+
         // ----------
         // Write
         // ----------
@@ -121,9 +129,16 @@ module debug_unit (
                     // enable/disable single step
                     ss_req = debug_wdata_i[0];
                     ss_resume_req = ~debug_wdata_i[0];
+                end
                 DBG_HIT:
                 DBG_IE:     dbg_ie_n = debug_wdata_i;
                 DBG_CAUSE:  dbg_cause_n = debug_wdata_i;
+                DBG_GPR: begin
+
+                end
+
+                DBG_CSR: begin
+
                 end
             endcase
         end