diff --git a/src/pcgen.sv b/src/pcgen.sv index 4b9f45c2e..80623583a 100644 --- a/src/pcgen.sv +++ b/src/pcgen.sv @@ -82,6 +82,8 @@ module pcgen ( // this tells us whether it is a consecutive PC or a completely new PC set_pc_n = 1'b0; + // keep the PC stable if IF by default + npc_n = npc_q; // ------------------------------- // 3. Control flow change request // ------------------------------- @@ -99,8 +101,8 @@ module pcgen ( if (if_ready_i && fetch_enable_i) // but operate on the current fetch address npc_n = {fetch_address[63:2], 2'b0} + 64'h4; - else // or keep the PC stable if IF is not ready - npc_n = npc_q; + + // we only need to stall the consecutive and predicted case since in any other case we will flush at least // the front-end which means that the IF stage will always be ready to accept a new request @@ -110,7 +112,7 @@ module pcgen ( // only predict if the IF stage is ready, otherwise we might take the predicted PC away which will end in a endless loop // also check if we fetched on a half word (npc_q[1] == 1), it might be the case that we need the next 16 byte of the following instruction // prediction could potentially prevent us from getting them - if (if_ready_i && branch_predict_btb.valid && branch_predict_btb.predict_taken && !npc_q[1]) begin + if (if_ready_i && branch_predict_btb.valid && branch_predict_btb.predict_taken && !fetch_address[1]) begin npc_n = branch_predict_btb.predict_address; end // ------------------------------- diff --git a/tb/core_tb.sv b/tb/core_tb.sv index fe6fab0ad..0255457ed 100644 --- a/tb/core_tb.sv +++ b/tb/core_tb.sv @@ -19,17 +19,17 @@ // import ariane_pkg::*; +import uvm_pkg::*; +import core_lib_pkg::*; `define DRAM_BASE 64'h80000000 + module core_tb; import "DPI-C" function chandle read_elf(string fn); import "DPI-C" function longint unsigned get_symbol_address(string symb); import "DPI-C" function longint unsigned get_symbol_size(string symb); - import uvm_pkg::*; - import core_lib_pkg::*; - logic clk_i; logic rst_ni; logic rtc_i; @@ -190,7 +190,8 @@ module core_tb; // initialize .bss bss_address = get_symbol_address(".bss"); bss_size = get_symbol_size(".bss"); - $display("Symbol Address: %x, Symbol Size: %x, Address: %x", ((bss_address - `DRAM_BASE) >> 3), bss_size, address); + // `uvm_info("Core Test", $sformatf(".bss address: %x, .bss size: %x, .tohost address: %x", ((bss_address - `DRAM_BASE) >> 3), bss_size, address), UVM_LOW) + // the section should be aligned on a double word boundary for (int i = 0; i < bss_size/8; i++) begin core_mem_i.ram_i.mem[((bss_address - `DRAM_BASE) >> 3) + i] = 64'b0;