diff --git a/src/ariane.sv b/src/ariane.sv index 16959fcb3..e5a8f7749 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -500,6 +500,8 @@ module ariane assign tracer_if.is_store = ex_stage_i.lsu_i.mmu_i.lsu_is_store_i; assign tracer_if.st_ready = ex_stage_i.lsu_i.store_unit_i.ready_o; assign tracer_if.ld_ready = ex_stage_i.lsu_i.load_unit_i.ready_o; + // exceptions + assign tracer_if.exception = commit_stage_i.exception_o; program instr_tracer (instruction_tracer_if tracer_if); instruction_tracer it = new (tracer_if); diff --git a/src/commit_stage.sv b/src/commit_stage.sv index 4dba4aafc..78b4dfebe 100644 --- a/src/commit_stage.sv +++ b/src/commit_stage.sv @@ -142,32 +142,4 @@ module commit_stage ( exception_o.tval = commit_instr_i.ex.tval; end end - - `ifndef SYNTHESIS - always_ff @(posedge clk_i) begin : exception_displayer - string cause; - // we encountered an exception - // format cause - if (exception_o.valid) begin - case (exception_o.cause) - INSTR_ADDR_MISALIGNED: cause = "Instruction Address Misaligned"; - INSTR_ACCESS_FAULT: cause = "Instruction Access Fault"; - ILLEGAL_INSTR: cause = "Illegal Instruction"; - BREAKPOINT: cause = "Breakpoint"; - LD_ADDR_MISALIGNED: cause = "Load Address Misaligned"; - LD_ACCESS_FAULT: cause = "Load Access Fault"; - ST_ADDR_MISALIGNED: cause = "Store Address Misaligned"; - ST_ACCESS_FAULT: cause = "Store Access Fault"; - ENV_CALL_UMODE: cause = "Environment Call User Mode"; - ENV_CALL_SMODE: cause = "Environment Call Supervisor Mode"; - ENV_CALL_MMODE: cause = "Environment Call Machine Mode"; - INSTR_PAGE_FAULT: cause = "Instruction Page Fault"; - LOAD_PAGE_FAULT: cause = "Load Page Fault"; - STORE_PAGE_FAULT: cause = "Store Page Fault"; - default: cause = "Interrupt"; - endcase - $display("Exception @%t, PC: %h, TVal: %h, Cause: %s", $time, commit_instr_i.pc, exception_o.tval, cause); - end - end - `endif endmodule diff --git a/src/util/exception_trace_item.svh b/src/util/exception_trace_item.svh new file mode 100755 index 000000000..2048d51df --- /dev/null +++ b/src/util/exception_trace_item.svh @@ -0,0 +1,54 @@ +// Author: Florian Zaruba, ETH Zurich +// Date: 17.06.2017 +// Description: Instruction tracer single exception item +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. +// +class exception_trace_item; + // contains a human readable form of the cause value + string cause; + logic [63:0] tval; + logic [63:0] pc; + + function new (logic [63:0] pc, logic [63:0] cause, logic [63:0] tval); + case (cause) + INSTR_ADDR_MISALIGNED: this.cause = "Instruction Address Misaligned"; + INSTR_ACCESS_FAULT: this.cause = "Instruction Access Fault"; + ILLEGAL_INSTR: this.cause = "Illegal Instruction"; + BREAKPOINT: this.cause = "Breakpoint"; + LD_ADDR_MISALIGNED: this.cause = "Load Address Misaligned"; + LD_ACCESS_FAULT: this.cause = "Load Access Fault"; + ST_ADDR_MISALIGNED: this.cause = "Store Address Misaligned"; + ST_ACCESS_FAULT: this.cause = "Store Access Fault"; + ENV_CALL_UMODE: this.cause = "Environment Call User Mode"; + ENV_CALL_SMODE: this.cause = "Environment Call Supervisor Mode"; + ENV_CALL_MMODE: this.cause = "Environment Call Machine Mode"; + INSTR_PAGE_FAULT: this.cause = "Instruction Page Fault"; + LOAD_PAGE_FAULT: this.cause = "Load Page Fault"; + STORE_PAGE_FAULT: this.cause = "Store Page Fault"; + default: cause = "Interrupt"; + endcase + + this.tval = tval; + this.pc = pc; + endfunction : new + + function string printException(); + string s; + s = $sformatf("Exception @%10t, PC: %h, Cause: %s\n\t\t\t\ttval: %h,", $time, this.pc, this.cause, this.tval); + return s; + endfunction + +endclass : exception_trace_item \ No newline at end of file diff --git a/src/util/instruction_tracer.svh b/src/util/instruction_tracer.svh index 0fafd1724..d5776aca7 100755 --- a/src/util/instruction_tracer.svh +++ b/src/util/instruction_tracer.svh @@ -85,14 +85,12 @@ class instruction_tracer; if (tracer_if.pck.translation_valid) begin // put it in the store mapping queue if it is a store if (tracer_if.pck.is_store && tracer_if.pck.st_ready) begin - // $display("Putting Store Mapping %0h \n", tracer_if.pck.vaddr); store_mapping.push_back('{ vaddr: tracer_if.pck.vaddr, paddr: tracer_if.pck.paddr }); // or else put it in the load mapping - end else if (tracer_if.pck.ld_ready) begin - // $display("Putting Load Mapping %0h \n", tracer_if.pck.vaddr); + end else if (!tracer_if.pck.is_store && tracer_if.pck.ld_ready) begin load_mapping.push_back('{ vaddr: tracer_if.pck.vaddr, paddr: tracer_if.pck.paddr @@ -122,6 +120,13 @@ class instruction_tracer; printInstr(issue_sbe, issue_commit_instruction.instruction, reg_file[commit_instruction.rd], address_mapping.vaddr, address_mapping.paddr); end + // -------------- + // Exceptions + // -------------- + if (tracer_if.pck.exception.valid) begin + // print exception + printException(tracer_if.pck.commit_instr.pc, tracer_if.pck.exception.cause, tracer_if.pck.exception.tval); + end // ---------------------- // Commit Registers // ---------------------- @@ -168,4 +173,11 @@ class instruction_tracer; $fwrite(this.f, {print_instr, "\n"}); endfunction; + function void printException(logic [63:0] pc, logic [63:0] cause, logic [63:0] tval); + exception_trace_item eti = new (pc, cause, tval); + string print_ex = eti.printException(); + $display(print_ex); + $fwrite(this.f, {print_ex, "\n"}); + endfunction + endclass : instruction_tracer \ No newline at end of file diff --git a/src/util/instruction_tracer_if.sv b/src/util/instruction_tracer_if.sv index 34ab3d1b5..c805037b0 100755 --- a/src/util/instruction_tracer_if.sv +++ b/src/util/instruction_tracer_if.sv @@ -46,10 +46,12 @@ interface instruction_tracer_if ( logic is_store; logic st_ready; logic ld_ready; + // exceptions + exception exception; // the tracer just has a passive interface we do not drive anything with it clocking pck @(posedge clk); input rstn, flush_unissued, flush, fetch, fetch_valid, fetch_ack, issue_ack, issue_sbe, waddr, - wdata, we, commit_instr, commit_ack, translation_valid, vaddr, paddr, is_store, st_ready, ld_ready; + wdata, we, commit_instr, commit_ack, translation_valid, vaddr, paddr, is_store, st_ready, ld_ready, exception; endclocking endinterface diff --git a/src/util/instruction_tracer_pkg.sv b/src/util/instruction_tracer_pkg.sv index 4add98817..147640690 100755 --- a/src/util/instruction_tracer_pkg.sv +++ b/src/util/instruction_tracer_pkg.sv @@ -21,5 +21,6 @@ package instruction_tracer_pkg; `include "instruction_tracer_defines.svh" `include "instruction_trace_item.svh" + `include "exception_trace_item.svh" `include "instruction_tracer.svh" endpackage \ No newline at end of file