diff --git a/.gitignore b/.gitignore
index 962e06663..43896084e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,5 @@
+*.swp
+*.swo
 site/*
 *.ucdb
 covhtmlreport/*
diff --git a/docs/07_cv32a60x/index.rst b/docs/07_cv32a60x/index.rst
index 6ec3fa794..8a737945e 100644
--- a/docs/07_cv32a60x/index.rst
+++ b/docs/07_cv32a60x/index.rst
@@ -4,5 +4,12 @@ CV32A60X documentation
 .. toctree::
    :maxdepth: 1
 
+..
    riscv/unpriv.rst
    riscv/priv.rst
+
+Below are links to RISC-V ISA documents tailored for OpenHW Group CV32A60X.
+Only those CSRs and Instruction Sets that are supported by the CV32A60X are documented here.
+
+| `Unprivileged RISC-V ISA <https://cva6-cv32a60x.readthedocs.io/en/latest/07_cv32a60x/riscv/unpriv.html>`_
+| `Privileged RISC-V ISA <https://cva6-cv32a60x.readthedocs.io/en/latest/07_cv32a60x/riscv/priv.html>`_