diff --git a/src/lsu.sv b/src/lsu.sv
index 294aa32a2..0061be143 100644
--- a/src/lsu.sv
+++ b/src/lsu.sv
@@ -46,7 +46,7 @@ module lsu #(
     output logic                     fetch_err_o,              // Instruction fetch interface
     input  logic [63:0]              fetch_vaddr_i,            // Instruction fetch interface
     output logic [31:0]              fetch_rdata_o,            // Instruction fetch interface
-    output logic                     fetch_ex_o,               // Instruction fetch interface
+    output exception                 fetch_ex_o,               // Instruction fetch interface
 
     input  priv_lvl_t                priv_lvl_i,               // From CSR register file
     input  logic                     flag_pum_i,               // From CSR register file
diff --git a/src/mmu.sv b/src/mmu.sv
index 8357b538e..764550721 100644
--- a/src/mmu.sv
+++ b/src/mmu.sv
@@ -210,6 +210,7 @@ module mmu #(
         fetch_gnt_o                   = instr_if_data_gnt_i;
         fetch_err_o                   = 1'b0;
         ierr_valid_n                  = 1'b0;
+        fetch_ex_o                    = '{default: 0};
 
         // MMU enabled: address from TLB, request delayed until hit. Error when TLB
         // hit and no access right or TLB hit and translated address not valid (e.g.