diff --git a/docs/old_doc/architecture.md b/docs/old_doc/architecture.md
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-# General Architecture
-
-## Scoreboarding
-
-The scoreboards main purpose is to decouple the check for data (WAW, WAR) and structural hazards and issue instructions to the various functional units. It does so by taking full responsibility for instruction issue and execution. This also includes detecting the two aforementioned hazards.
-
-The scoreboard enables utilization of all available functional units as well as efficient usage of pipelined functional units which take a couple of cycles before the instruction finishes. The scoreboard tracks all instructions which are currently being processed in all functional units.
-
-Because the scoreboard is in full control over the functional units it also controls the forwarding path and write back of all functional units.
-
-1. **Issue**: If a functional unit for the instruction is free and no other active instruction has the same destination register, the scoreboard issues the instruction to the functional unit. If a WAW hazard is present, the instruction issue will stall until the hazard has been cleared. Should the issue stage stall the instruction buffer in the ID stage fills until it is full.
-2. **Read operand**: The scoreboard monitors the availability of the source operands. A source operand is available if no earlier issued active instruction is going to write it. When the source operands are available (either through the register file or through a forwarding path from any of the other functional units or an already completed instruction), the scoreboard tells the FUs to proceed to read the operands. The scoreboard resolves RAW hazards dynamically in this step.
-3. **Execution**: The FU begins execution upon receiving operands. When the result is ready, it notifies the scoreboard. Any instruction can take multiple cycles.
-4. **Write Back**: Once the scoreboard is aware that the functional unit has completed execution, it commits the result in-order to either the architectural register file, CSR register file, floating point register file or data memory. If there are no structural dependencies on the write path the scoreboard can write more than one result at a time.
-
-The scoreboard maintains a connection to each functional unit and each architectural state holding element. For Ariane there is the plan to include the following FUs: ALU, Multiplier and LSU. If it should turn out to be necessary additional ALUs or multipliers can be easily added.
-
-**TODO: Detailed Bookkeeping**
-
-> While it will be possible that the execute stage houses more than one ALU or multiplier, this is not going to be the case for the load store unit (LSU). The current assumption will be, that the LSU is like any other functional unit (using a variable amount of cycles to perform its operation), but it should also be in full control over the data memories state. It therefore takes a special role in the whole design.
-
-Register addresses can be of type: CSR, Regfile (x0,.., x31), None (immediate), current PC
-
-**TODO: Register Encoding, OP encoding**
-
-
-### Exception Propagation
-
-In order to simplify hardware design exceptions are only considered at commit time. Therefore, the scoreboard provides an exception field. If an exception has been present prior to issue (for example in the fetch or decode step) it has been propagated to this point. An instruction that has the exception flag set is considered as completed by the scoreboard and can be retired as soon as every instruction prior to this one has been committed.
-
-### Scoreboard Implementation
-
-The scoreboard is implemented as a circular buffer with two pointers. The first pointer being the commit point. Everything above this pointer is save to be reused for new instructions arriving. The issue pointer points to the top of the buffer, e.g.: always to the latest issued instruction. The scoreboard therefore keeps track of instruction ordering.
-
-### Functional Units
-
-The FU are not supposed to have inter-unit dependencies for the moment, e.g.: every FU must be able to perform its operation independently of every other unit. The following interface is proposed to keep maximum interoperability. A minimum set of port definitions would be:
-
-| **Signal** | **Direction** | **Description** |
-|-------------|---------------|--------------------------------------------------|
-| clk_i | Input | Global clock signal |
-| rst_ni | Input | Reset the functional unit to a specific state |
-| operator_i | Input | Operation to perform |
-| operand_a_i | Input | Operand A |
-| operand_b_i | Input | Operand B |
-| result_o | Output | Result Output |
-| valid_i | Input | Data is valid from ID/Scoreboard |
-| ready_o | Output | Ready signal to ID/Scoreboard |
-| valid_o | Output | Data is valid to WB/Scoreboard |
-| trans_id_i | Input | Transaction ID for the operation to perform |
-| trans_id_o | Output | Transaction ID at which to write back the result |
-
-Refer to the [timing diagram](timing_diagrams/#functional-unit) section for further detail.
-
-### Branches
-
-Branches are handled by the branch unit in co-operation with the ALU. It is a little bit specially in the sense that it does not have a write back port to the scoreboard. Actually, the only thing the branch unit writes is PC + 4 (or + 2 in the compressed case) to the destination register. To save write back ports the ALU does this addition and the write back port of the ALU is used to write back to register *rd*. In summary, what this means is - branch instructions (including jumps) are another form of ALU instruction. They can only be performed if the ALU is ready (as the current ALU is single cycle this means always). Furthermore the exception write back port of the ALU is used to signal mis-aligned branch target exceptions (e.g.: an exception which occurs if the branch target is not aligned to a half-word boundary).
-
-The branch unit maintains two more connections to different parts of the processor:
-
-1. The issue and read operand stage: The issue stage will block if it issued a branch instruction which is currently not resolved. Therefore the branch unit will signal the issue and read operand stage that it just resolved a branch. This is only done if it was indeed a branch and not an instruction where branch-prediction just thought it was a branch.
-2. To the PCGEN stage where it signals whether this instruction was a branch, a taken and mis-predicted branch, a un-taken and mis-predicted branch, a taken and correctly predicted branch or an un-taken and correctly predicted branch. If it was a mis-predict the front-end (everything from issue to PCGEN) of the processor is flushed and PCGEN starts re-fetching from the newly calculated PC (which is correct).
-
-### LSU
-
-Loads can be issued immediately while stores need to wait for the commit signal from the scoreboard. They are kept in a store address queue (SAQ) for the time being.
-
-### Commit Point
-
-The scoreboard is the only way to update the architectural state. This simplifies the controller design significantly since this is the only point where an exception is known to be taken.
-
-### Issue Window
-
-Currently the idea is to not speculate past branches or jumps. So the issue window is the size of a basic block. Theoretically it could be possible to speculate past one branch.
-
-If the scoreboard encounters a branch it does not accept new instructions from ID. Executes the branch instruction. In the next cycle the speculated pc is compared to the calculated PC. If they match the scoreboard starts to issue instructions again. If not, a miss-predict is signaled and all fetched instructions are killed prior to the execute stage. The pipeline fills from the new address. Branch prediction data structures are updated accordingly.
-
-## Load Store Unit
-The load store unit is similar to every other functional unit. In addition, it has to manage the interface to the data memory. In particular, it houses the DTLB (Data Translation Lookaside Buffer) and the page table walker (PTW). It arbitrates the access to data memory, giving precedence to PTW lookups. This is done in order to un-stall TLB misses as soon as possible. A high level block diagram of the LSU can be found here:
-
-
-
-The LSU can issue load request immediately while stores need to be kept back as long as the scoreboard does not issue a commit signal: This is done because the whole processor is designed to only have a single commit point (the commit stage). Because issuing loads to the memory hierarchy does not have any semantic side effects the LSU can issue them immediately. Totally in contrast to the nature of a store: Stores alter the architectural state and are therefore placed in a store buffer only to be committed in a later step by the commit stage. Sometimes this is also called **posted-store** because the store request is posted to the store queue and waiting for entering the memory hierarchy as soon as the commit signal goes high and the memory interface is not in use.
-
-Therefore, upon a load, the LSU also needs to check its SAQ for potential data words. Should it find uncommitted data it stalls, since it can’t satisfy the current request. This means:
-
-- Two loads to the same address are allowed. They will return in issue order.
-- Two stores to the same address are allowed. They are issued in-order by the scoreboard and stored in the SAQ as long as the scoreboard didn’t give the grant to commit them.
-- A store followed by a load to the same address can only be satisfied if the store has already been committed (marked as committed in the SAQ). Otherwise the LSU stalls until the scoreboard commits the instruction. We cannot guarantee that the store will eventually be committed (e.g.: an exception occurred).
-
-For the moment being, the LSU does not handle misaligned accesses (e.g.: access which are not aligned at a 64 bit boundary). It simply issues a misaligned exception and lets the exception handler resolve the LD/ST. Furthermore, it can issue a load access exception.
-If an exception was signaled by the WB stage, the LSU kills all entries in its store queue except those that have been marked as committed.
-
-The LSU of the core takes care of accessing the data memory. Load and stores on words (32 bit), half words (16 bit) and bytes (8 bit) are supported.
-
-## D$ Interface
-
-| **Signal** | **Width (bit)** | **Direction** | **Description** |
-|---------------|-----------------|---------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
-| address_index | 12 | Out | Index into cache (send in cycle 0) |
-| address_tag | 44 | Out | Tag of cache (send in cycle 1:$) |
-| data_wdata | 64 | Out | Data to write into cache |
-| data_req | 1 | Out | Requesting a new transfer |
-| data_we | 1 | Out | This transfer is a write |
-| data_be | 8 | Out | Byte enable for the write transfer |
-| tag_valid | 1 | Out | Tag is valid |
-| kill_req | 1 | Out | Kill the outstanding request |
-| data_gnt | 1 | In | The request was granted, the sender can assume that it is safe to change the index, byte enable and write enable flag |
-| data_rvalid | 1 | In | Returned data is valid, the sender can now change the tag and tag request signals. Rvalid is also asserted for a write, in that case it just means that the tag can be changed |
-| data_rdata | 64 | In | Read data, this data is valid if the rvalid flag is asserted |
-
-
-
-The protocol that is used by the LSU to communicate with a cache works as follows:
-
-The LSU provides a valid index in *address_index* and sets *data_req* high. The memory then answers with a *data_gnt* set high as soon as it is ready to serve the request. This may happen in the same cycle as the request was sent or any number of cycles later. After a grant was received, the index may be changed in the next cycle by the LSU. In addition, the *data_wdata*, *data_we* and *data_be* signals may be changed as it is assumed that the memory has already processed and stored that information. After receiving a grant, the LSU provides the tag information by setting the *address_tag* and asserting the *tag_valid* signal. The memory answers with a *data_rvalid* set high if *data_rdata* is valid. The tag information may be unconditionally send by the LSU the cycle after it received a grant, e.g.: the cache needs to make sure that it is able to process the request. The cache can combinatorially use the tag address and tag signals (e.g.: doing tag comparison with it). This process may happen one or more cycles after the grant has been received. Note that *data_rvalid* must also be set when a write was performed, although the *data_rdata* has no meaning in this case. Check the [timing diagrams](timing_diagrams/#memory-interface) for further details.
-
-Furthermore, the LSU can kill the last outstanding request for which it should send the tag to the D$. It can do so by asserting *kill_req* with *tag_valid* at the same time. In that case the D$ will ignore the *address_tag* signal and clear its internal structures, ready to accept a new request in the same cycle.
diff --git a/docs/old_doc/block_details.md b/docs/old_doc/block_details.md
deleted file mode 100644
index d47d21192..000000000
--- a/docs/old_doc/block_details.md
+++ /dev/null
@@ -1,209 +0,0 @@
-
-# Block Details
-
-The processor has 5-stages:
-
-## Next PC Generation (PC Gen)
-
-PC gen is responsible for generating the next program counter. All program counters are logical addressed. If the logical to physical mapping changes a fence instruction should flush the pipeline, caches (?) and TLB.
-This stage contains speculation on the next branch target as well as the information if the branch target is taken or not. In addition, it provides ports to the branch history table (BHT) and branch target buffer (BTB).
-
-If the branch target buffer decodes a certain PC as a jump the BHT decides if the branch is taken or not.
-Because of the various state-full memory structures this stage is split into two pipeline stages. It also provides a handshaking signal to the decode stage to stall the pipeline if this should be necessary (back-pressure).
-
-The next PC can originate from the following sources:
-
-1. Exception (including interrupts): This also means to figure out to which exception handler the delegate registers are pointing to. If an exception is taken, disable interrupts.
-2. Debug
-3. Request from execute stage (jump, branch) which was not detected as one by the BHT.
-4. Predicted PC (BHT and BTB)
-5. Environment Call (`ecall) instruction. Read the CSRs to figure out where to jump.
-6. Miss-predict: This triggers a pipeline flush and the PC Gen stage starts fetching from there.
-
-### BTB and BHT
-
-Currently all branch prediction data structures reside in a single register like file. It is indexed with the appropriate number of bits from the PC and contains information about the predicted target address as well as the outcome of a two (actually configurable) saturation counter. The prediction result is used in the subsequent stage to jump (or not).
-
-For a future version a more accurate predictor might be necessary (gshare, tournament,...).
-
-
-## Instruction Fetch (IF)
-
-In the IF stage we already know the physical PC. The request of the instruction is on its way to the instruction memory. We know the result of the BHT and can set the next PC accordingly. At the end of this stage the instruction PC is passed on to the ID stage. Retrieved instructions are stored in an instruction queue.
-It is possible that a TLB or cache miss occurred. If this is the case the IF stage signals that it is not ready. The pipeline in the direction of the ID stage will empty itself.
-
-### ITLB
-
-
-### Instruction Queue
-
-The instruction queue is part of the IF stage. Its purpose is to decouple the instruction fetch unit as much as possible from the rest of the pipeline.
-
-## Instruction Decode (ID)
-
-The ID stage contains the instruction decode logic (including the planned compressed decoder) as well as the register files (CSR, floating point and regular register file). The decoded instruction is committed to the scoreboard. The scoreboard decides which instruction it can issues next to the execute stage.
-
-### Decoder
-
-The decoder's purpose is to expand the 32 bit incoming instruction stream to set the right values in the scoreboard, e.g.: which functional unit to activate, setting wright path and reading the destination, *src1* and *src2* register.
-
-The current privilege level is not checked in the decoder since there could be an operation in progress that sets the privilege level to the appropriate level.
-### Scoreboard
-
-The scoreboard's purpose was described in detail in the architecture section.
-
-
-
-The field functional unit can be of the following types:
-
-- CSR: Modify the CSR register using OP, OP can be of type:
- + MRET (check the current privilege level against the mret instruction, are we allowed to execute it?)
- + SRET (same as above but with sret)
- + URET (same as above but with uret)
- + ECALL (make an environment call)
- + WRITE (writing a CSR, we need to flush the whole pipeline after a write)
- + READ (we can simply continue with the execution, the worst that could happen is an access fault if we do not have the right privilege level)
- + SET (atomic set, flush the whole pipeline)
- + CLEAR (atomic clear, flush the whole pipeline)
-- ALU: Use the ALU to perform OP
- + ADD, SUB, etc. all arithmetic instructions. ALU always writes to the register file
-- LSU: Use the LSU to perform OP
- + LD, SD, LBU, etc. Loads are writing to the register file, stores are committed as soon as the store address and store data is known.
-- MULT: Use the Multiplier to perform OP
- + MULT, DIV, etc. all multiplier instructions are writing to the register file.
-
-The scoreboard also contains all exception information which occurred during execution. In particular those fields are:
-- exception cause
-- additional information like illegal instruction and faulting address
-- if it is valid or not
-
-If an exception already occurred in IF or ID the corresponding instruction is not executed anymore. Additionally a valid exception is never overwritten. For example an instruction fetch access fault is never overwritten by a load store access fault.
-
-### Issue
-
-The issue stage itself is not a real stage in the sense that it is pipelined, it is still part of the decode stage. The purpose of the issue stage is to find out whether we can issue the current top of the scoreboard to one of the functional units. It therefore takes into account whether the any other FU has or is going to write the destination register of the current instruction and whether or not the necessary functional unit is currently busy. If the FU is not busy and there are no dependencies we can issue the instruction to the execute stage.
-
-
-### Compressed Decoder
-The compressed decoders purpose is to expand a compressed instruction (16 bit) to its 32 bit equivalent.
-
-
-## Execute Stage (EX)
-
-### Read Operands
-
-The read operands stage is still part of the scoreboard but conceptually lies at the boundary between ID and EX. The operands where read in the previous cycle but we can still use forwarding to get the source operands from either:
-
-1. Register file
-2. Scoreboard (Forwarding)
-4. Immediate field
-
-The scoreboard and forwarding are mutually exclusive. The selection logic is a classical priority selection giving precedence to results form the scoreboard/FU over the register file.
-
-To obtain the right register value we need to poll the scoreboard for both source operands.
-
-### Write-Back
-
-The write-back stage writes the results from the FU back to the scoreboard. They are committed in-order in the next stage.
-
-## Commit Stage (Commit)
-
-The commit stage is the single commit point in the whole architecture. Everything prior to this stage was just computed in a temporary fashion. This is also the only point where an exception can occur.
-The commit stage is entirely decoupled from the rest of the pipeline. It has access to the scoreboard which issues finished instructions in-order to the commit stage.
-
-### CSR Register File
-
-The CSR register file contains all registers which are not directly related to arithmetic instructions. It contains the following registers supervisor registers:
-
-| **Register** | **Address** | **Description** |
-|--------------|-------------|-----------------------------------------------------------|
-| sstatus | 0x100 | Supervisor status register |
-| sedeleg | 0x102 | Supervisor exception delegation register (maybe external) |
-| sideleg | 0x103 | Supervisor interrupt delegation register (maybe external) |
-| sie | 0x104 | Supervisor interrupt-enable register (maybe external) |
-| stvec | 0x105 | Supervisor trap handler base address |
-| sscratch | 0x140 | Scratch register for supervisor trap handler |
-| sepc | 0x141 | Supervisor exception program counter |
-| scause | 0x142 | Supervisor trap cause |
-| stval | 0x143 | Supervisor bad address or instruction |
-| sip | 0x144 | Supervisor interrupt pending (maybe external) |
-| sptbr | 0x180 | Page-table base register |
-| tlbflush | ? | Flush TLB |
-| cflush | ? | Flush Cache |
-
-And the following machine mode CSR registers:
-
-| **Register** | **Address** | **Description** |
-| ------------------- | -------------- | ------------------------------------------------------ |
-| mvendorid | 0xF11 | Vendor ID |
-| marchid | 0xF12 | Architecture ID |
-| mimpid | 0xF13 | Implementation ID |
-| mhartid | 0xF14 | Hardware thread ID |
-| mstatus | 0x300 | Machine status register |
-| medeleg | 0x302 | Machine exception delegation register (maybe external) |
-| mideleg | 0x303 | Machine interrupt delegation register (maybe external) |
-| mie | 0x304 | Machine interrupt-enable register (maybe external) |
-| mtvec | 0x305 | Machine trap handler base address |
-| mscratch | 0x340 | Machine register for machine trap handler |
-| mepc | 0x341 | Machine exception program counter |
-| mcause | 0x342 | Machine trap cause |
-| mtval | 0x343 | Machine bad address or instruction |
-| mip | 0x344 | Machine interrupt pending (maybe external) |
-| mcycle | 0xB00 | Machine cycle counter |
-| minstret | 0xB02 | Machine instruction-retired counter |
-| Performance Counter | 0xB03 -- 0xB9F | Machine performance-monitoring counter |
-
-We need to be careful when altering some of the register. Some of those registers would potentially lead to different behavior (e.g.: mstatus by enabling address translation).
-
-## MMU
-
-
-## LSU
-
-### Memory Arbiter
-
-The memory arbiter's purpose is to arbitrate the memory accesses coming/going from/to the PTW, store queue and load requests. On a flush it needs to wait for all previous transactions to return. We currently do not have another way to squash load and stores that already went into the memory hierarchy.
-
-### Store Queue
-
-The store queue keeps track of all stores. It has two entries: One is for already committed instructions and one is for outstanding instructions. On a flush only the instruction which has the already committed instruction saved persists its data. But on a flush it can't request further to the memory since this could potentially stall us indefinitely because of the property of the memory arbiter (see above).
-
-The store queue works with physical addresses only. At the time when they are committed the translation is correct. Furthermore the store queue directly outputs the address and value of the instruction it is going to commit since any subsequent store also needs to check for the address.
-
-# Cache
-
-## Interface
-
-```verilog
- input logic clk,
- input logic rst_n,
-
- // Data Port (TLB or CORE )
- input logic [DATA_WIDTH-1:0] data_wdata_i,
- input logic data_req_i,
- input logic [BE_WIDTH-1:0] data_be_i,
- input logic data_we_i,
- input logic [ADDR_WIDTH-1:0] data_add_i,
- input logic data_abort_i,
- input logic [ID_WIDTH-1:0] data_ID_i,
- output logic data_gnt_o,
-
- output logic [DATA_WIDTH-1:0] data_r_rdata_o,
- output logic data_r_valid_o,
- input logic [ID_WIDTH-1:0] data_r_ID_o,
- input logic data_r_gnt_i,
-
- //Service Port (32bit)
- input logic conf_req_i,
- input logic [31:0] conf_addr_i,
- input logic conf_wen_i,
- input logic [31:0] conf_wdata_i,
- input logic [3:0] conf_be_i,
- input logic [PE_ID_WIDTH-1:0] conf_id_i,
- output logic conf_gnt_o,
-
- output logic conf_r_valid_o,
- output logic conf_r_opc_o,
- output logic [PE_ID_WIDTH-1:0] conf_r_id_o,
- output logic [31:0] conf_r_rdata_o,
-```
diff --git a/docs/old_doc/fig/ariane_overview.pdf b/docs/old_doc/fig/ariane_overview.pdf
deleted file mode 100644
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+++ /dev/null
@@ -1,4742 +0,0 @@
-%PDF-1.5
%
-1 0 obj
<>/OCGs[6 0 R 50 0 R 93 0 R 137 0 R 181 0 R 225 0 R 269 0 R 313 0 R 357 0 R 401 0 R 445 0 R 489 0 R 533 0 R 577 0 R 621 0 R 665 0 R 709 0 R 753 0 R 798 0 R]>>/Pages 3 0 R/Type/Catalog>>
endobj
2 0 obj
<>stream
-
-
-
-
- application/pdf
-
-
- Druck
-
-
- 2017-06-29T10:52:22+02:00
- 2017-06-29T10:52:22+02:00
- 2017-04-04T19:25:41+02:00
- Adobe Illustrator CC 2014 (Macintosh)
-
-
-
- 256
- 184
- JPEG
- /9j/4AAQSkZJRgABAgEASABIAAD/7QAsUGhvdG9zaG9wIDMuMAA4QklNA+0AAAAAABAASAAAAAEA
AQBIAAAAAQAB/+4ADkFkb2JlAGTAAAAAAf/bAIQABgQEBAUEBgUFBgkGBQYJCwgGBggLDAoKCwoK
DBAMDAwMDAwQDA4PEA8ODBMTFBQTExwbGxscHx8fHx8fHx8fHwEHBwcNDA0YEBAYGhURFRofHx8f
Hx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8f/8AAEQgAuAEAAwER
AAIRAQMRAf/EAaIAAAAHAQEBAQEAAAAAAAAAAAQFAwIGAQAHCAkKCwEAAgIDAQEBAQEAAAAAAAAA
AQACAwQFBgcICQoLEAACAQMDAgQCBgcDBAIGAnMBAgMRBAAFIRIxQVEGE2EicYEUMpGhBxWxQiPB
UtHhMxZi8CRygvElQzRTkqKyY3PCNUQnk6OzNhdUZHTD0uIIJoMJChgZhJRFRqS0VtNVKBry4/PE
1OT0ZXWFlaW1xdXl9WZ2hpamtsbW5vY3R1dnd4eXp7fH1+f3OEhYaHiImKi4yNjo+Ck5SVlpeYmZ
qbnJ2en5KjpKWmp6ipqqusra6voRAAICAQIDBQUEBQYECAMDbQEAAhEDBCESMUEFURNhIgZxgZEy
obHwFMHR4SNCFVJicvEzJDRDghaSUyWiY7LCB3PSNeJEgxdUkwgJChgZJjZFGidkdFU38qOzwygp
0+PzhJSktMTU5PRldYWVpbXF1eX1RlZmdoaWprbG1ub2R1dnd4eXp7fH1+f3OEhYaHiImKi4yNjo
+DlJWWl5iZmpucnZ6fkqOkpaanqKmqq6ytrq+v/aAAwDAQACEQMRAD8A9U4q7FXYq7FXYq7FVCyP
7lv+Ms3/ACdbFVfFXYq7FUl0+381p5m1OW+uYJfL0kcX6LgQUmikFRLz+AVDdR8R/oqnWKuxV2Kq
Fyf31p/xlP8AyafFVfFXYq7FVC5/vrT/AIyn/k0+Kq+KuxV2KpR5stfMlzoc0Plu7jstXZ4jDczc
eCoJVMoPKK4G8YYD4PpHUKq+gx61HpoTWZY5r8SzlpIqcDEZnMNKKlKRcQdvpPXFUwxV2KuxVQtv
767/AOMo/wCTSYqr4q7FXYq7FXYq7FXYq7FXYq7FUOLC3BahkXkzMQJZQKsSx2DeJxVJ/LWk6xFF
etq+pG/M13M9p6fqw+hDyKrB/evz4cdm2O+Kpz9Rh/ml/wCR0v8AzVirvqMP80v/ACOl/wCasVUJ
7SNZbYK8oDyFWHrS7j03P83iMVV/qMP80v8AyOl/5qxV31GH+aX/AJHS/wDNWKu+ow/zS/8AI6X/
AJqxVy2UCyLJV2ZDVeUkjAEgjozEdDiqvirsVdiqyWGOVQHr8JqpUlSDSmxUg9Diqn9Rh/ml/wCR
0v8AzVirvqMP80v/ACOl/wCasVSbV9F1KXWdHubPVZbSyglkF5Y/vHFyHjagZ/VUrx41Wn7W5rSm
Kpz9Rh/ml/5HS/8ANWKu+ow/zS/8jpf+asVULO0jaJizzE+pKKmaXoJGA/a8MVV/qMP80v8AyOl/
5qxV31GH+aX/AJHS/wDNWKqkUMcSkJX4jVixLEmlNyxJ6DFV+KuxV2KuxVj83n3yrb3FxbXeoQ2c
9qyxzpdOsFGcIVAMpQN/eoKrUVIHXFVqfmD5PedoF1S2MqsVK+qnUNw61pTn8NenLbrirBvqH5RX
d9qstvrXo3mtT3KXbCeEtNNMiSu1t66PskMkdTB8DJT1OYxVkvkqDQobi5vdK8zXuvwENA8Mt7Dd
20JaVpwESJVCMok4r/kcR0AxVlv1+L+VvwxVoahGSfgYUNO2+2Kt/X4v5W/DFUul+q6hpF5p8/qL
DeC6glZCAwWV3QlSa70O22Ku8vWGlaBo9vpOnpILS25cPUbm5aR2kdmJ7s7k+HhtiqY/X4v5W/DF
UNdahH69p8Df3x8P99SYqifr8X8rfhirvr8X8rfhirHvLXljRfL2p6zqNk9xJPrk63F2JjEVVl5U
CcERqfGftlj9GKsh+vxfyt+GKtNqEYUngxoK0FMVS9/OXlyOaeCW+hhmtmRJ45ZEjZTIeMdQ5Gzt
8KnudhviqHi/MDyhKCYtTt3AuDaMVkQgThuBQ77fF8O+1fnirGLPyv5e1GGNNH84ax9XS0jjhj0/
UojGsBSaKOVVRWWrFyQ/80a0+yQVWeQXUcUEcRMkpjVVMkhBduIpyYim574qqfX4v5W/DFUr1nzJ
Y2HpT3QdIYHLu4HLb03GwFSTU9AMkI2LYmVGksvfzX8lWQU3F8qiSRYYytXDyuWAjTgG5PWNgVG4
74eHzRxeSVa9pvk7z/bWGrPNdtatayRWzwCJVeG4lgnJZJ45DXlapSoHfbwIx2g5KZXZ69bCFh6b
/wB7Ke3eRj44+GV8UK3+ILb/AH2/4f1x8Io8UIPV/OumaVp8t/dRy/VoBylKLzYL3PEGpp4DfIyj
TOEuJJL786PI9krvPcSFInaOZ0jZwjRwG4evEGvGNSTSu+3XIW3GA70o1by9omuzrqVtrev6Sty7
XLjS7mOxMvrKlPWZYxNIEC/AJGPCpAoNsHE2DTk9UVp+g6VZ6ymrNrWv3kqOJEt7u99WBWDFm4xk
DiH5UZRtQDbHiX8uWXf4ps/99Sf8L/XHiX8uUFZ/mFol5e3tlbpM11p7Kl1GyFOJkXmtC1AwI7rX
HiYjCT1ULvyp5avppbjUNJtLqe5ULcmeGOQPQqfiVgVJrGm/X4V8Bkmlcvlbywju6aRZK8h5SMLa
IFiHaWrHjv8AvHZvmSepxVQk8keT5JrKY6NZpJppJsjHCkfp1j9IqAgUcSm3E7dNthiqYafpGk6d
6o0+ygs/Xb1J/q8SRc3AC8n4AcjQUqcVReKtLyq1elfh+VB/HFW8VULL+5b/AIyzf8nWxVXxV2Kp
PeaFaatc6RqU2sG2ksG+sC2glaOKUulOFwgkHqKrUYV7jwJBVQWufmF5V8v3VtZavesl5eeqbSK3
t7i4MqQuVZlWBJugFeuKqFl+avkS9WN7XUjJFNHNNDKILji8ds4jmZax9EZgPftXFW9K/NX8v9Wu
7Wz07WI7m4vZmtrVEjmo8qRCZlDFAvwowqa0rt12xVleKtPy4Nx+1Q8fniqBufL2gXVz9ZudNtZ7
kihnkgjd6clenJlJ+1GrfMA9sVUo/K3liNJEj0iyRJZluZVW2iAadSGWVgF3cEAhuuKq2m6Foell
jpmnW1iXUI5toY4eSqzMqngFqA0jEe5PjiqOxV2KpNrcMc80cNxGssMhKtG4DKymN6gg7EZdj5NO
Tmgl0TRlYuthbBy/qlhEgPqBmbnWn2uTsa+JPjllBqsom2tra1t47e2iSC3iUJFDGoRFUdFVVoAB
7YVatv7s/wDGST/k42AKVXCqTecGuE8u3j29y1pMqFkuVQSFCN6hS8Q+91HiRlWbk5Gm5n3MGj8y
RlY7hPNNw7vJb8VOnOUYTHkqUChPjjIVmBopFdt641Odx/0vsTrTtG80nSIePmZ55ZrY0u5rKMMZ
JPjSX0wy8ePKnDwoK7GotmIyrmyW3jaKCON3Mjoqq0h6sQKEnr1wNoY35budRk81eY4bq5WWOF4P
SgRpWWMMrEfbYqpZOPIKB8VThLVAniKzQiV87eZF4u0jrbF5AOMSgR/u13Y8mYNUmnb5YnkiP1F6
K6x2+iXd99RW9u4FuZRAqAySvGzkIKK7VYigoD8sscJIvJ3mXUdc1nUdP1LyjJo8FkoMGoSpIYLk
lqfuvWtrZqcaHcV6im2KsltERInRFCqJZqKBQD963YYqrYq7FWl5VavSvw/Kg/jireKqFl/ct/xl
m/5OtiqpPPBbwvPPIsUMSl5JXIVVUbksx2AGKpVq/mzQ9K0ptVuZy+nIYudzAjTIFmZVRgYwwYfv
F+zU4qnGmvcyadayRm6KPDGyEfVgKFQRTl8X34qpW/Lg/Lly9WWvLjy/vG68fh+7FVXFXAAAACgH
QYq7FWn5cG4/aoePzxVvFXYq7FXYq7FUp1Tl9cgr05fD8vTf+OXY+TRk5rMta3YqlWqax+iNJkvf
qV3qHCYp9VsIvWnPOYrUJVdlrVt9hkbpNW1Y6/NdXi250m+tkbkPrE8aLGKc6Gqux34Dt+0v+VxQ
VMUwuq8F/wBbf7jlefk5Wi+v4IbMR2iT+Z4/MsljCvl+e3trozp68t1Xj6NCGCUST4y3GlR474Qw
ndbKPlNNet472z13VYNVvoJlMckKpEywNCgX1YkVeDPIsj0369cSsL5EofQIraLzh5l9KQGaQ2sk
0XFV41iIU/CanlvuR9+E8mEPqKh5YkEvnDzVIjhl52qKFIKgpGynegNeQ3HjiUQ+qT0LUfLln5g8
vHS7+SRIjdCcyQlQ/qW136yULKwpzjFdsscJBaL+XsWmapaajLr+s6o9kD6FvqF0s0IYwLblyojQ
liq1rX7RY/tHFU7t/syf8ZZv+TrYqq4qoyXcMcpiPMuFDEKjvsxIG6gj9k4qpi5eSaOKIlWlcjlJ
FJQKIye/Deq+OKsO81/mto/lefUI9TS49PTmijluI4IeDyzRvKkUXO6R2YpE37NPfFWXWbSC1tJ1
cPBen1FUoUcCVWm3+Nx7Yql3n5ZG8la4sZ4ubKYchxqBwNSOSuKgdNsVQ35dRRN5M0pTHSNbW0KJ
JUkcbaIqTyqeQpX54qn1qbOO1t0kEKyFFWjWchbkFqQTXc7YqvtF4xEAAD1JCAFKChkYiincDFVb
FXYq7FWnDFGCmjEGh98VbxV2KuxV2KuxVKdVDC8gqdi23y9N8ux8mjJzQtyiO8CuoZTIagio+w2W
FrC76paf75j/AOBH9MaW1G2tLX0z+5j/ALyT9kfzt7YgJJVvqlp/vmP/AIEf0xpFoaSKOOZxGqoO
MZIUAV+34ZTm5OZo/q+H6msxXZqVx/dj/XT/AImMKChrbTNPt9Uu7yC2jiu7pI/rVwigPLx5BfUY
btxGwr0xQALYHrGpnRLrzdeWRltLxZLBY7ma7E4meVq8UhkSX0V/eFe/sFAGSDjylRNJ75bWc+c/
NMjwxorfU1jnC8ZH4xNUNVFJCk7Hk2As4fUXp5srU7yQxu9AGcqCTTbqRljhIDSLGyNu1beP/df7
C/74j9sVTRERFCIoVR0UCgH0DFW8VUE/3um/4xRf8SkxVe8CuauTs3NCrMpB48eqke+Koa79KB7c
vPJGjyFWLTSAH927UqW8VxVAw+ZvKLpDcDWbZlk9RoDJdjcxCktFd+sfKj7fD3xVMZY9P1bTGTkt
1p99ERzieqSRSL1V0PRlPVTiqzSrO3sopLO2Xhb27JFChJaiJDGFFWJJ28TiqrdAmezPhMSf+RMg
xVXd1jRnc0VAWY+w3OKu5N/vqX/kVJ/zTiruTf76l/5FSf8ANOKrXmEaM7xyhEBZj6UmwG5/ZxVc
6lkZQaEggH54q3irsVdiroYUmvo45OXD0pGorMu4ZAPskeOKrfTWO5uY1J4JIAoZi1AY0PViT1OK
pVqizG9gEcTzMzFuKAEgBGHQkfhlsJABqnEkpXrMPmr1LA6Vp5YC5X679YRhxgKsGdOLCrDsvfxG
E5AxGMppFb38knprZzByCwDhUqAQDTkw8Rh8QI8MpbpEHmOAXMWuwQwTCeRrVYDUNAXPB2+N6M38
vb3wwlazjTJ9I0yynsEllQtIzSVPNx0kYDofAZVKRttjEUizoOlEkmCpNASXftWn7XvkSbZx25MT
uo0iu540FESWRVBJNAGNBvlR5uwxG4hD6l5d81XtrZyaSYoFaaGW4MwV+VtUM4QBhxk6cSdvEYRF
pnnHRMB5d1cTM/obFVA+NOoLe/vjwsvzEbSR9F0WdZWlsLd/rTLLcc4oz6jp9lnqDyK9ici2iIPR
dBpOnW97d31vbpFeX3D63Ooo0npLxTl/qrtjaeEMzReKha1oAK/LLXWoLR/952/55/8AJiPFUdir
sVUE/wB7pv8AjFF/xKTFVZVoWNa8jX5bAfwxVvFUth8teXYYRDHplqsYEg4+jGa+t/e1qN/U/b/m
74qj4YYYIUhhRYoYlCRRIAqqqiiqqjYADoMVU7b++uv+Mo/5NJirrqCSVoGjcI8MnMcl5A1RkpQF
f5sVSjzJZ+aJre3Omahb2qxSl78SQFxLbiNw0YXnWpYrQhlp13+yVWU61qZ0vSbvURaXF8bWNpRZ
2cZluJSo+xFGKcmPYYq8b8r6xouga/rGq2mh+cmu/VmudU0K3iNzYi9vPSmZ1iT0naRkmHH1PhAB
NNlOKvYmuzeaAbswS2xuLT1TbXChJo+cfLhIoLBXWtGFeuKoWReUbLWlQRX54qlWp6suk2tlN+gp
9YS5nu1uWs4fWmiWFJpkbhxo3MxCNauvxMMVSaH8yLaZtL4eQfMEaajcNbyGbTFRrdV4qJpgrPxQ
s/7RHwhj2AZVMdM83W2pala2cXk/VbSOeWKOW7vrFYIY1ltXuSxILn92yLE9QBzagJxVONDmje5t
kUMONq3VGUdY+hIAxVjP5heZvMmhziXQtOi1QvdKl7bl6TKrQxhCi8kFORqzM3wgdDXZVPrB5J9U
hlgaGSVIzJNGJPhWq8CAyq1dz4DD0Y9WE+fPyv8Ay8VZdV131rGS5urm+mvbaeX1nmdBO55R28jh
YktgyKKAca7tuQyeg+Xdcsdeih1LTJIptPWIKkkZkH9/HDPH8MkcVB6Tqfpp40VQ/mKaGPUF9R1S
sS05ED9pvHLcTVl6Jl5fZX0mJlIZS0tCDUf3rZCXNnHkmORZPPtSNp+kbvlNRvXlqPVYUPM9uWVn
m5uKuELfPHnHTNB0by3Y3U17b/pQxcLu0ilmjRIVj5fWGhmt5kRjKtCj9etVqDY4ZQv5OXthBc65
oJ813/mXVbObndJqMV1G8Ch2jAiNw8v7v4QPtVqCT9oYoRcf92nyH6sqLsocg2RUEeOKSyhAAigG
oAAB8RlrrEFo/wDvO3/PP/kxHiqOxV2KqCf73Tf8Yov+JSYqqqAGehqSan22GKrsVdirsVULb++u
v+Mo/wCTSYqqsAWSpoQaj32OKtuiyIyOKq4KsPY7HFXcW/37L/yNk/5qxVRUyG7kQzS8VjjYD1ZO
pZwf2vYYqqPCJEZHklKOCrD1ZNwdj+1ircgBjYE0BBBPhtiq+2urq2i9JIUkUM7BzIVPxuX6BG6c
vHFVX9J3v/LNH/yOb/qnirv0ne/8s0f/ACOb/qniqjpiGO7gjO5S3dTT2aMYq6T/AHtu/wDjIv8A
yaTFUPC8yazGsDIGlVlcupagA5bAMu/wjD0YjmwbX/OvmqZ7xNS8hfpXTrFr0WTm3url5LiASRRB
YGtSVFyjBfVQsgVzuwDYGTOvKTy/orTZDp0OkC/tfrtxpccJheC4l4SSI/2fjDSMHqgJOKta9/ve
v/GJf+JNluLq05eiY6D/AMcuL/Wl/wCTrZCXNsjyR+RZPLvMugT3/mNbxNRmtobeaQS2sYXjLSQs
Kt9paHf4TvQV2qDAlzcUbiGYWXma0gs4IHt5y0UaIxUR0JVQDSrjDxBoOCSt/iyy/wCWa4+6P/qp
jxBfAkxhAQig9QADkC5sRQbPQ1xUsoUKFAXdaDifbLXWJMmradpOlPe6hMILZXt4zIQzfHLHFGgo
oJ3dgMVTCx1Swv7WK6tZg8EzOkTkFOTRsysAGCnYo33YqisVUE/3um/4xRf8SkxVWULVqda/F86D
+GKt4q7FXYqoW399df8AGUf8mkxVWYLVa9a/D86H+GKrLl2S3lddmVGZT7gVxVjmq+bLrS729t5N
C16+W2qYX061E/qKHRPtPFDFybnzUJI/wg8uLDjiqW2/5jWk9+Ug8uebJFkuPqQu102NoCY5CjSc
wfhRGY8manQ9wcVRug+c59bvJbeLQfMOlRQ2kty95rFmlpF6kfDjCvwtyY8iTuOm1eyrK5ApRg2y
0NT7Yq3irsVdiq1Lq1tLsXF1MlvAkMnOWVgiCrxgVZiAKk0xVjP5geeB5Rf63JptxfW1xciKaSDf
0v3CFKqod2Z22FFp1JIpuqmskV1dXcTWyyxzmL1GVWRWQmgKkk9fi7HJiq3YG72W3v6QsYllvr57
WJjxWSa5ijUtxLUBZgK8VJ+Qx9K+pfYHVLitxZXTXQUcPUSaCZRzVZKVqwFVKt8qY+lfUtu/r4ui
L3kZeC8S3p041bp6fv45ZCujXkvqm+mxSzaA0UU720sgnWO5iCGSNi7gOgkWRCy9RyUjxByqXNtj
ySX8pNe1nX/IGm6rrM63OpTvdLPOihFb0rqWJCoVIxTgg3C79ciyQt//AL33X/GaT/iZyuXNz8P0
hQyLa7FXYq0aUNenfCgsoXjxHH7NBx+WWusYH578ryanpsKabbQale2pkjUahFIY6GFousEa8/j4
h6n7HKm9BiqP/LvyVo3luxs7C3tvRuJ2M2pIgneE3LQUlaKS5Bl48k+EFvxxVkkF9GYYywlLcRyP
pSGpp7LiqDOp872+jt45RcRwRem0sE4iLt6hXcL8QB+1TFUL5Y1DzE9tdP5iigiuWuXNrHYxXJAt
qL6Ym9QN+968uB4+GKpz9dh/ll/5Ey/804q767D/ACy/8iZf+acVXwSmSJGZTGzor8D4MKgjpiqy
2/vrr/jKP+TSYqrNxqtetfh+dD/DFVO7VmtZlUVYowAHckHFUt84WOoayLR9I1640Se15sJEtrmV
WdihRnjWSBH4FCOMgZSGO3fFUlm0Xz5PZLaN+YMy3kfCRrmPRo0PIGcg8FIHEs0VVJ3EdDXm2Ksr
t7iaPRJLS8vZNRvmSYG5+qtAG9RmKKEVeKhFYIN+1Sa4qqyceDcvs0PL5Yqh725trVJ7q6EjWtpa
XF1KkRIciHixpQrU0rTfFWIzfnH+WUWnWt16l7JcXSxMNORJzcRmVIJOMlWEQKLdxcqSHrtWhoqy
uw1HR9Sht7/SJnms5frMRZjL/eW0whkHGXeqyIy1pv22xViP5yz6Unki/g1GS2VLtEhhju3CJJJ9
ZgcKoM9nydVQuAZQPh+Kq8sVTDzz5y8u+VJFu9as5ZLe7mEIuYoo2jiKwRlfVd2QIG6LiqcQSm2v
FmsLbi8sP7yL0WLCpU7hKUpt1yYAIYEkFA+a9FtfNlhFYa/pb3dpBMtzFGq3kHGVAQr8oJI2qAx7
48I714j3IzRopNFtGtNN08wQM5kZfSuXPIgD7UjM1AqhVFaKoAFAAMeEd68R7ll+8l5dc7yFQ6oq
qjRMhAqxr8da1yyADXMlOdKt2k8vm3gle0aQTpHPAI+cZaRwHQSK8fJTuOSkeIOVS5tseTE/yB/8
lNoh4SJU3Z4yusj/AO9k3VkVF+QA2yLJE3/+991/xmk/4mcrlzc/D9IUMi2uxV2KtGlDXp3woLKF
KlQV2Wg4j2y11iV3RAsg3FX4zXLBXHJSVExFR33GKqrwz2VLuGO3Lwh2+GL06fu23J5NXftiqPjQ
IioOigAV9tsVUU/3um/4xRf8SkxVWUrVqda/F86D+GKt4qp29xb3MEdxbSpNbzKHimjYOjqwqGVh
UEEdxiqFunuY4opoGVY44ZpYkdS1I2EZQUDLxDFWpX+GKq9t/fXX/GUf8mkxVWYrVa9a/D86H+GK
t4qtMoDlAruwAJCI70BrSvEHwxVQRnF5K/ozcTHGAfRl6hnr+z74qrrIrMVoysoBKurIaGtDRgPD
FW5CoRi260NR7YqqWf8Ax04/+MMv/E48VYpJpn5wQ31xcW7+X72T1LhLG9vVnS5itZ5ZXWDlBEo4
oFtqj9ri1STxIVZHNbXfoaZFqMvq30dsRdTRM0avMBGJGHDhsWqQKYqqadAkepoVLmsMn2nd/wBu
P+YnFUv1i/0yy1GX6/qcViZ5QLdJpII+bJAjNw9UVYqu5p0xVZJc2tvPKLiWWWG6t2iLo0aN8dPi
RgY/2e4yYjYYGVFhGpflr+X2oJcLNNqMf1mGSCU2506AcZY4I2ISKNUBpaR/s+ODgK8YRcHkrylD
q9pq8eqa6t/aBYhMl/GhltYwojtZSjKXiXgtf2mIq7MceArxhlWoXttqd160YdVRFSnMA1qx/wB1
ufHvlmONNeSVpvpcNy3l4xWkqw3LCdYJ5VMyo5kfizIWQuAeo5CviMrlzbY8m/KugnQNCt9KNy94
YGlb6xIXLN6srSUrI8r0XnxFWOwyLJjWptxu7xuvGWU0+THKzzc7EagmEejWMt/Np0Wr28moWyLJ
cWahTNGj/YZ4xJyUN2JG+S4Wn8we5Tj0mzubW5uLHVYLxbXmsvohZAskYqUYrIeLDuDjwr+YKXZW
5jRpQ16d8KCyhCCoIFAQCB4Za6xKrv8A3h/563X/ABGbFUff/wC8Nz/xif8A4icVV8VUE/3um/4x
Rf8AEpMVVlIJYAUoaH32BxVqWNJY3jcVRwVYVIqCKHcYqgtN0DR9N061060tVWzsolgto3rKUjQU
VechdyAPE4qqXECQaZNGlSFhYVO5NEoK/QMVVLb++uv+Mo/5NJiqsxAKgitTQe2xOKt4qlWqebtM
8t3ds2oLIU1O4t7GJ4+FEdxM/N+boeICGvDk3tiqUaj/AM5A/lPYGNZtZZpJIoLhY0tbqvo3IVkk
JMSqBwkDEE17U5bYqnVh5o0XXYYdY0maS6068t0a2nEE68lWWVCeLorj4lPUe/TFUTJfQBGJSUgA
kj0Zd/8AhcVc9zbsQaTqwqAyJOhoeoqoBptiq314v57v77rFW1uLcNzP1h2AIBdbh6A0rTkD4Yqi
dOnSTU0ChxSGT7SOn7cf8wGKpF5v8m6R5nmlt9WhSaG3nSWA/vY5UcRR7pLDJE61p2OKpnY3Mdlq
J+sMqxiEonpRMAKFSBQF+3TJUSGNgFhdp5S83W1r6I/Me9mb1Hm5zWLv8fppFEoPqB/TRUJZOXxM
eR+LcjhK8QR2iaZ52t7hLrUvPb3DyXkNzeWqaavpG3jTi1pGzfYDncyoisfCuPCV4gyDWLpbq9D2
sg4LGqsXjfryY7VKZbjBDXkIKceX+Q0mLkQW5S1IFB/et2qcrlzbI8kxyLJ53rP1D63f8/S5+pNy
5ca15HrXIHm5kK4Er/Nzyzosuq2s/wDg/UtcudWEqahqmkXEsU1tFHEtvyaOvoyt6cpWNJNqc+nx
Vm4aZ+TNI8tRG+nsfK19oF9ZWLRi4u1ZIp47veT06OUeQtZo0vJAwJB/aNVVXKXaNHoa4UFlCNyU
NSlQDT55a6xLzGksUUTiqSXFwrAEjYiYHcb4qvv7KH6jcfFL/dP/ALtl/lP+Viqv9Sh/ml/5HS/8
1YqoJZQ/Xpvil/uov92y/wA0n+ViqqtpCSwrKOJp/fS77A/ze+KrvqUP80v/ACOl/wCasVd9Sh/m
l/5HS/8ANWKtPYW7qUYylWBDAyy7g/7LFW7b++uv+Mo/5NJiqszUKileRp8tif4Yq3irdrcxW91M
0vIK6RhSqO+6l6/ZB/mGKov9LWXjJ/yJl/5pxVByzJPevLHy4enGtWVk3DOTswHiMVakbjGzUrQE
0+WKt4q7FXYqvsv+Okn/ABhk/wCJR4qxD8xPIx82zCIXL2UljciWG5iejfFAiuvBkdN12DHcb064
qq+YpNat9LvP0PaW9zrNta00y0uLhljlkV4x8bM9tWiE9X+nJWQGNAlKptd89DTLh4vJdo19HBAb
dDrkVJLiWJWlHDZVSFyymstWI22PIDiK8IRFzqnm2MxND5ZtZxLAryQ/pSNPRme3VuBkMp9T07hX
R6ItVZWUmjDHiK8ITb1JWhtHEMUN3JawyX1qtwZlhnYHmgccw3FqivemW4yS15AAyXy/yOkxcgA3
KWoBqP71u9BlcubZHkmORZMF1JQ15dqejSyj72OVnm52IXBMP8Uap/LB/wAA/wDzXh42H5bzWT+Y
9SmhkiZYQsilCQj1owp/PjxL+W80syDktE0BPhhQWUKxZQxFCRUj55a6xBR/8e//ADFT/wDM3FVe
/wD94bn/AIxP/wAROKq+KoRQ8msrAOaJIicpV4dhMafFU9R4YqxrzD5r80abr2o6XYeVtT1S3s4I
pbbUomVIJnlG6V+rtQIdjw5t/k0qQqyueK5t7azmf1GnmKrPbq0bKpMbMwDFISaMvWg+WKrfrM3/
ACyy/fF/zXiqpBMJo+YUpuylWpUFWKnoSOoxVTtv766/4yj/AJNJiqszEFRT7RofuJxVvFXYq7FX
Yq07FUZgKkAkD5Yq3irsVdiropkgvUlk5cPTkWqqz7lkI2UHwOKqEjXEt1cSwOqRO4KepE9TSNVJ
3ZO48MVS+9F6Z6NJHsAARGw9/wCfL8fJoyc0OrTrOqOysrKzfCpU1UqO7N/Nk2tWwqpW392f+Mkn
/JxsAUp3pWq2NtYpDM7LIrSEgRyHrIxG4UjocolE25EZCkU3mDSV3aVh/wA8pf8AmnIkVzZx9WwY
VqQZ7i7uYpKo0ksiA+oKgsSNuY/VlR5ubCJEW/q8fi//AAb/ANcDdToBRpVqSFegqSf2VPU4oCrg
ZNE0BOFBZQpYqCwoxFSPfLXWIKP/AI9/+Yqf/mbiqvf/AO8Nz/xif/iJxVXxVBTwQvqERu/TFlJx
VmZyhDIkreA8R+1irDfNbee7fUdTHlrStLu9PgSA6Z9YuD6lw7wymbk312EJ6cqxgVTcMd+4VZrc
22lwNbPpwie4aQqy+sT8PpuT3k7jwxV0lxeo0amGMmRuI/ettRS3++/8nFVOye+9Fv3MX97L/u1v
9+t/xXiqvaxzK0zShVMj8lCMWFAiruSF/lxVWYsCtBsT8XyocVbxV2KpT5q8yWXlrQbrW72OSW1t
PT9RIjEr/vJFjFDM8MfVxWrjFU2BqAfHFWnLBGKirAGg98VbxV2KuxV2KuxVAXSTS3YjjQu/H4VX
qR3JrsBU9cuhIANM4klv/D+qNIkv7laKw4s7V+Iqd6IR+zj4q+EoT29xbuEnjMZO61oQQPAioycZ
AsJQIQ1t/dn/AIySf8nGwhiVXCqjdV4L/rb/AHHKc/Jy9F9fwWrpGp3ds5gt2ZXUhXJVQajanIio
9xmMIlzZ5o8l9xpeo26GSa3ZYx1cFWA+fEtT6ceEpjniUBF/eTf64/4guBtCrgS0a0NOuFBZQvLi
OX2qfF88tdYgVbikL8WZUuZi3FWYgEyjooJ6nFW7+9h+o3Hwy/3T/wC6pf5T/k4qr/XYf5Zf+RMv
/NOKqF/ew/Ubj4Zf7p/91S/yn/JxVVW9jq1VlpX4f3MvSg/yfHFV312H+WX/AJEy/wDNOKqbzLLP
bBFk+GQsxaN1AHpuOrADqcVY9r3nOLy9faLZzRRumtX8lmju06uJHnCII+EEsLMeZNJJY9h8PLsq
yzFUiu9J1SbV7jU1umGm28TpJp629u3qyeiSrtPKxkQIXBAjVTUbkjbFU9xV2KsG/Ouz0+4/LnUn
vQqrbtBJFPxjLxOZkj5RmV4lVmV2SvNdmPyxVnINQDiqW+YBqzWSppBi/SDSAQ+uZhDsCW9T0A0h
HEHYdfEdcVV9NFysJjunD3Kems7IsqRmT0kMhjSZnkVC5JUMx+eKovFXYq7FXYqh0vWs79pGQvG6
BSBTlQGoIr71r/ZkxGw1mVFJNY8m/lhrN1NcanYtPcXXxTVe8Xlx9T9lGC/8fD9PH2FBwllxBONS
1CG6jihgRlhhbkrv1NFKigO9KN33yyECN2ucwdkstv7s/wDGST/k42WBqKrhVQu6mMDrvvX5HKc3
JytILkR5IGHyboU7zTDzXr9pPcNI8ofUnWhkjlj4oZFZFAE1VEdKFEP7OUgtksZHMLZPJ+l297b3
q+dPMV29tbrbC0TUBJBLwj9L1JQsfAy/tMxO7b4krHGTyXwCjSjwcf8AEFysufEUq4GTRrQ069sK
CyheXEcvtU+L55a6xDQP6dpLJSvB52p0rSRjiqIudO1SW2liVIA0iMoJlelSKf77xVdNDfwwyTSR
xenEpd+MjE0UVNAYxv8ATiqhf/7w3P8Axif/AIicVVl5VavSvw/Kg/jireKuxV5r+Ynly31DWPJm
qSNP62na2UhitLVrqR/Vn9RuberEkMKrb8pZCjEDpTeqr0CfUIYYpJCsh9NWbeOQD4RXrx/HFXlU
X5g6pqn5o6Np1tJqem6XqemzX02lXMCRo9La4FJlK+pGytGjcuZVtth1Kr1/FXYqwH88orQfl3e3
09gupS6dLBPa20k08EfqvKsHNjbywOeKzMacsVZy1wkXFXDlqA/CjuPvUNirBPzC886fbaXqltba
tLoeoaWbaSfUXhmCRJcMFVgVt7rkW5ceHp1/1R8QVZT5Tmkn8v2E8t8NTkltbSR9SAKi4ZrWImYK
wUj1K8qEVGKpvirsVdirsVQF4jtcPVlREjMjSSMERI1+0zMegGWwlQapxspUdW8oeuOfmrS454ys
DW/rRFhJOA0SAGVWLOEqg4/EOmDxV8JFRtFNawXltPDd2N0OVteW0glhkH+S42PTLIzthKFKdt/d
n/jJJ/ycbJBgVXCqjdV4L/rb/ccpz8nL0X1/BDojuwRFLO2yqoqSfYDMV2ZkBuUzsvKuosn7544A
WZqbyMKsSKgUX/hslwuMdR3BXPlCZObJdq7MeXFoyo6AdQzU6eGHhYjUHuS+90u+s950Hp1oJUPJ
K/gR9IyJi3QzCSDNaGnXtgbSyhQwUBjVgNz75a6xCJ/vBcf61x/xN8VYp+a3m7y5HOmjX3mDUPLd
1p8tvdG5seYEy3MNyI1cxOGMMfoNJKrUqFAXcjFWQ+XPOXlzzF5cuY9Fvm1BbSxUy3RjuI1cMJYg
wNzylarW7/aZj0JY1qVUff8A+8Nz/wAYn/4icVVlDAtU7E/D8qDFW8VdirDfNukahqjaBFb2jTwW
etLf3MqrBIEWCVwOSzT2zD7fLnHzZeP2GrTFWZYqkd3oGm3GqTa3O85urBZFghEKPEC1sycg5ieV
TxmIPCRQduQNMVTzFVryRxgF2CgmgqaVPhiqUeZ9Cl1/S/0emoapo4Z1d7rTA0FwVXfh6jROVUnr
xofelQVU19VF4q/KMmgX1VZOR9uQFT8sVSrzXoNtrmlnSpxGYruRfUWaBrmNgilqPFG0bkEJSqup
HUHFUVolhHp1hHp0btIljHBbLI6uhYQ28aV4yFm3p3J+ZxVH4q7FXYq7FUFPMYbmTnGk8M0Zjlgk
3R422IOx9+oPU5ZGNhrlOily6L+Xa3frf4XtPrL+lJy+qWxAa1HCFlqaK0YeikAGmDwynxAiJvqT
WdvYWtlDZ6baf7zWkaIqKACBRFARaBj8K7ZZCFNc8l8lJI0jXiihFFaKooNzU9Msa12KqN1Xgv8A
rb/ccpz8nL0X1/BHeV2hF/IH/vGj/ck+xq4+dKfjmPFytTeylqNv+aaeZLqbSrrSZPL8wg9C3vhN
68JQqJ+PootfUUvTk5oeO1K5NxUtt/8Ale8rWUk48uQBLh11CEfXCHtwECvERzPItzK8iNuNQDVQ
qyu0bUl8uqfMn1b6+IiL/wCo8/QLbj9z6vx77UB3rikMNU3AdUkZSWRieKkbig7k+OVOx3ZcqlVC
k1IFCfllrrULEjvZTolObNOFqaCpkelSAcVTAavcGZovq6VVVYn1DSjFh/J/k4qh5tVnu7X0FgVP
rcDlWMhPEEAb/B/l4qp3/wDvDc/8Yn/4icVVGZIlklkcLGKuzMaBVCipJPTpiqUW/nfyZcyrDba9
p88rlVVIrqFyWdS6D4WO7KpZfEAntiqIsfM3lu/ultLHVbO6u2jE628FxFJIYjuJAisW4mvWlMVR
dl/ct/xlm/5OtiqvirBdQn85x/mPxihLeTnsm+tSi6t4uF4IJQrNA5M8i0ZV4xgCpDEnjTFWcu3F
S1CeIJoBU7eAxVfcWN+dHlbTZI49WmiHp3LEFQTQkKxSUKKfZPBgOpVu6rCH1r83/wBKny/FeeWx
r6wtfxWsq37q1iCYUkkkVYwztMQH4KgWlaHlxVVO/LFr+a6XgTzPcaNdadLR7j6qs/rKWjcPFEGS
NPTEnp8S9W48q1qKKoD81Z9Z0ry+0nl6Qwaj6kUlkyxzT+mySDmBFBHcOwKNsvpsOtfhxVNfLNy1
1o9tO4kWSSG3MqTMzSq/1aLkJC8cDFgevKNDX9kdMVTTFXYq7FXYql18pE9a9QCP1Zfj5NGXmgm/
3rj/AOMb/rTJtarhV2KuxVRuh8C+zfwOU5+Tl6L6/ghgSCCDQg1BGxBHcZiuzItMbfzBqkK8fUWV
RsPVWpFPdSp++uS4miWnHRs+btTL8BHCPj4V4t/Jzr9rHiYfl/NCXV7d3TA3ErSU+ypoFH+xFB9O
RJtvhiEeSDcVuEH+Q/61xZHmy0KF+EdBsPoy11qhZf3Lf8ZZv+TrYq5P97pv+MUX/EpMVUrW39S0
tJFkaN0hVQV47hlUn7Qb+XFVt/bzfUbj/Spf7p+0X8p/yMVeR6h+ZfnaPzjF5NuNIMlzqc8qCtI4
Xsw/plo7hRIrSLFVnDKm+wP2S5pXpVr5E8rWzLJb6bawyqEAdbS0DgRxmJPiEVfhjYoN/skjpgVE
23lXRbW+a/tbaGC+cBXu4re2SUqBQAyLEGpT3xVNIYhFHwBLbkljSpLEsTtTucVX4q8h/Mbzb+be
ieYhb6PZx3en308UWmzxW7TpbVWha6UcZOLMfidTxUV2rSpV6tpxvjYW5vwi3vpr9YERJTnT4uJI
GBUXBdzWyiMJ6sCiiqDR1A7CuxH3YqwD81/IR83XOnalpurT+XtWtFa2nuo45meW3kYMsRe3boJN
xv3wJBZ/aXUdpY29naRTTR28aRRS3DULLGoUF2ashY03JXc4UML/ADQ1HztYaOmpeXEju7mF2a+t
m4o0sKxtxjiL8lX4zyNdzuAQSMIVb+VOtedda8tHUvNUCW088pNpAYJLW4SJRxZZ4nLANzDcSp3W
laHbEqzPArsVdirsVS+/UCeo7qCf1Zfj5NGXmgW/3rj/AOMb/rTJtarhV2KsI/Mzzh5k8rW0Gpad
pxvtNiSVtQMaetIp+FYz6fOI8AWqzBq+3UrGRplEAo/yZr2sa/5XtdW1SzSykumMtvHGzMDC1fTY
8lRgSvYjKsx9LlaQes+5OcxXZuxVDf7v/wCe3/MnCw6/juROBmxbyhqetX93qy6lJFPFa3tzb2cs
a+mfTVk+AqC32aijVqfDuZFpxyJJt6kepyxwUHBOsKtHIsnL1JDtHIwo0jMN1UjocVWSTn12liZ1
LKqsHt5m+yWIpTj/ADYqhkh4IqLLKFUAKBFebAf89MVU7qzS6tpbaaWYwzKUkCpeoSrChHJZQw+g
4quFrGJTMGcTMAGk9G75EDoCedcVX8G/39L/AMirz/qpiruDf7+l/wCRV5/1UxV3Bv8Af0v/ACKv
P+qmKu4N/v6X/kVef9VMVdwb/f0v/Iq8/wCqmKu4N/v6X/kVef8AVTFXcG/39L/yKvP+qmKtNDyF
GllIqDT0rzqDUf7s8RirfBv9/S/8irz/AKqYq7g3+/pf+RV5/wBVMVdwb/f0v/Iq8/6qYq7g3+/p
f+RV5/1UxV3Bv9/S/wDIq8/6qYq7g3+/pf8AkVef9VMVdwb/AH9L/wAirz/qpiqEvEb1R+9kPw94
7odz4vl2Pk05OagnJH5h2LUIBaKdtjSvVj4ZNrVPXm/n/wCSEv8AXCtO9eb+f/khL/XFaWyM0i8Z
OLqCCA1tIRUdDucVWXM83AfH3/3xKP45Tm5OVo/q+CH9aX+b/kjJ/XMZ2N/inetL/N/yRk/rit/i
mkqZFO7MXLseDIAOBX9rFQisDNjXlDSr/T5dR+ux+m93e3VzH8QYGOQx8SAGfj06VyRaccSDu9g+
qW/8n4n+uWOC19Tt/wCT8T/XFXfU7f8Ak/E/1xV31O3/AJPxP9cVd9Tt/wCT8T/XFXfU7f8Ak/E/
1xVjGsXXnOz19o9O0CDVNCaCDhMLpba4W4acrNyEhZWRYSHFADUEb12VSdfMv5oevwP5dgxGMuJf
0xagCT0gRFSjFqy1XnQfDvTtirMtEivJ9HsptWtFtNTkgje9tUfmscxUF0VgzAhW2rU4qjfqdv8A
yfif64q76nb/AMn4n+uKu+p2/wDJ+J/rirvqdv8Ayfif64q76nb/AMn4n+uKu+p2/wDJ+J/rirvq
dv8Ayfif64q76nb/AMn4n+uKu+p2/wDJ+J/rirvqdv8Ayfif64q76nb/AMn4n+uKu+p2/wDJ+J/r
iqnJpljI3J46kCn2m/gckJEMTEFb+h9O/wB8/wDDN/XDxlHhh36H07/fP/DN/XHjK+GHfofTv98/
8M39ceMr4YeeWd9+aa28CXvki3luXu41nnhv4o40tGnlWRxG00jF0hjjb7e5f7PwkF8Qr4YTTSJv
N2oapYwan5NXSNOcO9/dPqMVyYyIFZY0SJlJJndl5bjitf2vhjKRPNnD0mwyv9AaT/vj/h3/AOas
jwht8aXe79AaT/vj/h3/AOaseEL40u936A0n/fH/AA7/APNWPCF8aXe79AaT/vj/AId/+aseEL40
u9Sby9pv1qNhb/uwjhjzf7RKcf2vY48IXxpd7//Z
-
-
-
- uuid:a13ff8b1-8e66-0b4b-b70e-682c3e294938
- xmp.did:97e54639-65ab-4645-971c-9c1d9204d341
- uuid:5D20892493BFDB11914A8590D31508C8
- proof:pdf
-
- xmp.iid:97f151c3-b4a7-4a9a-923a-d346af292d3e
- xmp.did:97f151c3-b4a7-4a9a-923a-d346af292d3e
- uuid:5D20892493BFDB11914A8590D31508C8
- proof:pdf
-
-
-
-
- saved
- xmp.iid:97f151c3-b4a7-4a9a-923a-d346af292d3e
- 2017-04-04T18:59:08+02:00
- Adobe Illustrator CC 2014 (Macintosh)
- /
-
-
- saved
- xmp.iid:97e54639-65ab-4645-971c-9c1d9204d341
- 2017-04-04T19:25:42+02:00
- Adobe Illustrator CC 2014 (Macintosh)
- /
-
-
-
- Print
- False
- False
- 1
-
- 29.700008
- 21.000156
- Centimeters
-
-
-
-
- MyriadPro-Regular
- Myriad Pro
- Regular
- Open Type
- Version 2.106;PS 2.000;hotconv 1.0.70;makeotf.lib2.5.58329
- False
- MyriadPro-Regular.otf
-
-
-
-
-
- Cyan
- Magenta
- Yellow
- Black
-
-
-
-
-
- Standard-Farbfeldgruppe
- 0
-
-
-
- Weiß
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 0.000000
-
-
- Schwarz
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 100.000000
-
-
- CMYK Rot
- CMYK
- PROCESS
- 0.000000
- 100.000000
- 100.000000
- 0.000000
-
-
- CMYK Gelb
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 100.000000
- 0.000000
-
-
- CMYK Grün
- CMYK
- PROCESS
- 100.000000
- 0.000000
- 100.000000
- 0.000000
-
-
- CMYK Cyan
- CMYK
- PROCESS
- 100.000000
- 0.000000
- 0.000000
- 0.000000
-
-
- CMYK Blau
- CMYK
- PROCESS
- 100.000000
- 100.000000
- 0.000000
- 0.000000
-
-
- CMYK Magenta
- CMYK
- PROCESS
- 0.000000
- 100.000000
- 0.000000
- 0.000000
-
-
- C=15 M=100 Y=90 K=10
- CMYK
- PROCESS
- 15.000000
- 100.000000
- 90.000000
- 10.000000
-
-
- C=0 M=90 Y=85 K=0
- CMYK
- PROCESS
- 0.000000
- 90.000000
- 85.000000
- 0.000000
-
-
- C=0 M=80 Y=95 K=0
- CMYK
- PROCESS
- 0.000000
- 80.000000
- 95.000000
- 0.000000
-
-
- C=0 M=50 Y=100 K=0
- CMYK
- PROCESS
- 0.000000
- 50.000000
- 100.000000
- 0.000000
-
-
- C=0 M=35 Y=85 K=0
- CMYK
- PROCESS
- 0.000000
- 35.000000
- 85.000000
- 0.000000
-
-
- C=5 M=0 Y=90 K=0
- CMYK
- PROCESS
- 5.000000
- 0.000000
- 90.000000
- 0.000000
-
-
- C=20 M=0 Y=100 K=0
- CMYK
- PROCESS
- 20.000000
- 0.000000
- 100.000000
- 0.000000
-
-
- C=50 M=0 Y=100 K=0
- CMYK
- PROCESS
- 50.000000
- 0.000000
- 100.000000
- 0.000000
-
-
- C=75 M=0 Y=100 K=0
- CMYK
- PROCESS
- 75.000000
- 0.000000
- 100.000000
- 0.000000
-
-
- C=85 M=10 Y=100 K=10
- CMYK
- PROCESS
- 85.000000
- 10.000000
- 100.000000
- 10.000000
-
-
- C=90 M=30 Y=95 K=30
- CMYK
- PROCESS
- 90.000000
- 30.000000
- 95.000000
- 30.000000
-
-
- C=75 M=0 Y=75 K=0
- CMYK
- PROCESS
- 75.000000
- 0.000000
- 75.000000
- 0.000000
-
-
- C=80 M=10 Y=45 K=0
- CMYK
- PROCESS
- 80.000000
- 10.000000
- 45.000000
- 0.000000
-
-
- C=70 M=15 Y=0 K=0
- CMYK
- PROCESS
- 70.000000
- 15.000000
- 0.000000
- 0.000000
-
-
- C=85 M=50 Y=0 K=0
- CMYK
- PROCESS
- 85.000000
- 50.000000
- 0.000000
- 0.000000
-
-
- C=100 M=95 Y=5 K=0
- CMYK
- PROCESS
- 100.000000
- 95.000000
- 5.000000
- 0.000000
-
-
- C=100 M=100 Y=25 K=25
- CMYK
- PROCESS
- 100.000000
- 100.000000
- 25.000000
- 25.000000
-
-
- C=75 M=100 Y=0 K=0
- CMYK
- PROCESS
- 75.000000
- 100.000000
- 0.000000
- 0.000000
-
-
- C=50 M=100 Y=0 K=0
- CMYK
- PROCESS
- 50.000000
- 100.000000
- 0.000000
- 0.000000
-
-
- C=35 M=100 Y=35 K=10
- CMYK
- PROCESS
- 35.000000
- 100.000000
- 35.000000
- 10.000000
-
-
- C=10 M=100 Y=50 K=0
- CMYK
- PROCESS
- 10.000000
- 100.000000
- 50.000000
- 0.000000
-
-
- C=0 M=95 Y=20 K=0
- CMYK
- PROCESS
- 0.000000
- 95.000000
- 20.000000
- 0.000000
-
-
- C=25 M=25 Y=40 K=0
- CMYK
- PROCESS
- 25.000000
- 25.000000
- 40.000000
- 0.000000
-
-
- C=40 M=45 Y=50 K=5
- CMYK
- PROCESS
- 40.000000
- 45.000000
- 50.000000
- 5.000000
-
-
- C=50 M=50 Y=60 K=25
- CMYK
- PROCESS
- 50.000000
- 50.000000
- 60.000000
- 25.000000
-
-
- C=55 M=60 Y=65 K=40
- CMYK
- PROCESS
- 55.000000
- 60.000000
- 65.000000
- 40.000000
-
-
- C=25 M=40 Y=65 K=0
- CMYK
- PROCESS
- 25.000000
- 40.000000
- 65.000000
- 0.000000
-
-
- C=30 M=50 Y=75 K=10
- CMYK
- PROCESS
- 30.000000
- 50.000000
- 75.000000
- 10.000000
-
-
- C=35 M=60 Y=80 K=25
- CMYK
- PROCESS
- 35.000000
- 60.000000
- 80.000000
- 25.000000
-
-
- C=40 M=65 Y=90 K=35
- CMYK
- PROCESS
- 40.000000
- 65.000000
- 90.000000
- 35.000000
-
-
- C=40 M=70 Y=100 K=50
- CMYK
- PROCESS
- 40.000000
- 70.000000
- 100.000000
- 50.000000
-
-
- C=50 M=70 Y=80 K=70
- CMYK
- PROCESS
- 50.000000
- 70.000000
- 80.000000
- 70.000000
-
-
- C=6 M=30 Y=16 K=0
- CMYK
- PROCESS
- 6.469825
- 29.944304
- 16.253909
- 0.000000
-
-
- C=25 M=6 Y=5 K=0
- CMYK
- PROCESS
- 25.094986
- 6.344701
- 5.035477
- 0.000000
-
-
-
-
-
- Graustufen
- 1
-
-
-
- C=0 M=0 Y=0 K=100
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 100.000000
-
-
- C=0 M=0 Y=0 K=90
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 89.999400
-
-
- C=0 M=0 Y=0 K=80
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 79.998800
-
-
- C=0 M=0 Y=0 K=70
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 69.999700
-
-
- C=0 M=0 Y=0 K=60
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 59.999100
-
-
- C=0 M=0 Y=0 K=50
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 50.000000
-
-
- C=0 M=0 Y=0 K=40
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 39.999400
-
-
- C=0 M=0 Y=0 K=30
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 29.998800
-
-
- C=0 M=0 Y=0 K=20
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 19.999700
-
-
- C=0 M=0 Y=0 K=10
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 9.999100
-
-
- C=0 M=0 Y=0 K=10
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 9.999100
-
-
- C=0 M=0 Y=0 K=5
- CMYK
- PROCESS
- 0.000000
- 0.000000
- 0.000000
- 4.998800
-
-
-
-
-
- Strahlende Farben
- 1
-
-
-
- C=0 M=100 Y=100 K=0
- CMYK
- PROCESS
- 0.000000
- 100.000000
- 100.000000
- 0.000000
-
-
- C=0 M=75 Y=100 K=0
- CMYK
- PROCESS
- 0.000000
- 75.000000
- 100.000000
- 0.000000
-
-
- C=0 M=10 Y=95 K=0
- CMYK
- PROCESS
- 0.000000
- 10.000000
- 95.000000
- 0.000000
-
-
- C=85 M=10 Y=100 K=0
- CMYK
- PROCESS
- 85.000000
- 10.000000
- 100.000000
- 0.000000
-
-
- C=100 M=90 Y=0 K=0
- CMYK
- PROCESS
- 100.000000
- 90.000000
- 0.000000
- 0.000000
-
-
- C=60 M=90 Y=0 K=0
- CMYK
- PROCESS
- 60.000000
- 90.000000
- 0.003100
- 0.003100
-
-
-
-
-
-
- Adobe PDF library 10.01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
endstream
endobj
3 0 obj
<>
endobj
8 0 obj
<>/Resources<>/Font<>/ProcSet[/PDF/Text]/Properties<>>>/Thumb 803 0 R/TrimBox[0.0 0.0 841.89 595.28]/Type/Page>>
endobj
800 0 obj
<>stream
-HWrWCk_ eY8J᠁ )~eLL7@ a"8eU峿gߜuTv*Mʨ7g_UFs5Xu*}RV\5Պ_M