diff --git a/verif/env/corev-dv/custom/cvxif_custom_instr.sv b/verif/env/corev-dv/custom/cvxif_custom_instr.sv index efb0a593e..573e801bc 100644 --- a/verif/env/corev-dv/custom/cvxif_custom_instr.sv +++ b/verif/env/corev-dv/custom/cvxif_custom_instr.sv @@ -105,7 +105,7 @@ class cvxif_custom_instr extends riscv_custom_instr; has_imm = 1'b0; end endcase - endfunction + endfunction function void pre_randomize(); rd.rand_mode(has_rd); @@ -114,6 +114,16 @@ class cvxif_custom_instr extends riscv_custom_instr; imm.rand_mode(has_imm); endfunction + virtual function bit is_supported(riscv_instr_gen_config cfg); + cva6_instr_gen_config_c cfg_cva6; + `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6") + return cfg_cva6.enable_x_extension && ( + instr_name inside { + CUS_ADD_MULTI,CUS_NOP,CUS_ADD_RS3, + CUS_EXC,CUS_U_ADD,CUS_S_ADD + }); + endfunction + endclass `endif // __CVXIF_CUSTOM_INSTR_SV__ diff --git a/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv b/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv index 314a3078d..6a4308d2e 100644 --- a/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv +++ b/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv @@ -11,6 +11,8 @@ // Add custom instruction name enum CUSTOM_1, + +//Custom instruction for CVXIF CUS_ADD, CUS_ADD_MULTI, CUS_NOP, @@ -18,3 +20,7 @@ CUS_ADD_RS3, CUS_EXC, CUS_U_ADD, CUS_S_ADD, + +//Zicond extension +CZERO_EQZ, +CZERO_NEZ, diff --git a/verif/env/corev-dv/custom/riscv_zicond_instr.sv b/verif/env/corev-dv/custom/riscv_zicond_instr.sv new file mode 100644 index 000000000..0fc06102b --- /dev/null +++ b/verif/env/corev-dv/custom/riscv_zicond_instr.sv @@ -0,0 +1,78 @@ +// Copyright 2023 Thales +// Copyright 2023 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +`ifndef __RISCV_ZICOND_INSTR_SV__ +`define __RISCV_ZICOND_INSTR_SV__ + +/** + * This class describe Zicond extension. + */ +class riscv_zicond_instr_c extends riscv_custom_instr; + + `uvm_object_utils(riscv_zicond_instr_c) + `uvm_object_new + + virtual function string get_instr_name(); + get_instr_name = instr_name.name(); + return get_instr_name; + endfunction : get_instr_name + + // Convert the instruction to assembly code + virtual function string convert2asm(string prefix = ""); + string asm_str; + asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); + case (instr_name) + CZERO_EQZ: asm_str = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + CZERO_NEZ: asm_str = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + endcase + return asm_str.tolower(); + endfunction : convert2asm + + virtual function bit [6:0] get_opcode(); + case (instr_name) inside + CZERO_EQZ, + CZERO_NEZ : get_opcode = 7'b0110011; + endcase + endfunction + + virtual function bit [2:0] get_func3(); + case (instr_name) inside + CZERO_EQZ : get_func3 = 3'b101; + CZERO_NEZ : get_func3 = 3'b111; + endcase + endfunction + + virtual function bit [6:0] get_func7(); + case (instr_name) + CZERO_EQZ, + CZERO_NEZ : get_func7 = 7'b0000111; + endcase + endfunction + + function void pre_randomize(); + rd.rand_mode(has_rd); + rs1.rand_mode(has_rs1); + rs2.rand_mode(has_rs2); + endfunction + + virtual function bit is_supported(riscv_instr_gen_config cfg); + cva6_instr_gen_config_c cfg_cva6; + `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6") + return cfg_cva6.enable_zicond_extension && ( + instr_name inside { + CZERO_EQZ, + CZERO_NEZ + }); + endfunction + +endclass + +`endif // __RISCV_ZICOND_INSTR_SV__ diff --git a/verif/env/corev-dv/custom/rv32zicond_instr.sv b/verif/env/corev-dv/custom/rv32zicond_instr.sv new file mode 100644 index 000000000..4b35cefa5 --- /dev/null +++ b/verif/env/corev-dv/custom/rv32zicond_instr.sv @@ -0,0 +1,13 @@ +// Copyright 2023 Thales +// Copyright 2023 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +`DEFINE_ZICOND_INSTR(CZERO_EQZ, R_FORMAT, ARITHMETIC, RV32X) +`DEFINE_ZICOND_INSTR(CZERO_NEZ, R_FORMAT, ARITHMETIC, RV32X) diff --git a/verif/env/corev-dv/cva6_defines.svh b/verif/env/corev-dv/cva6_defines.svh index 4ce0352ce..05afb59bc 100644 --- a/verif/env/corev-dv/cva6_defines.svh +++ b/verif/env/corev-dv/cva6_defines.svh @@ -13,3 +13,8 @@ `define DEFINE_CVXIF_CUSTOM_INSTR(instr_n, instr_format, instr_category, instr_group, imm_tp = IMM) \ class riscv_``instr_n``_instr extends cvxif_custom_instr; \ `INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp) + +// Zicond extension instruction +`define DEFINE_ZICOND_INSTR(instr_n, instr_format, instr_category, instr_group, imm_tp = IMM) \ + class riscv_``instr_n``_instr extends riscv_zicond_instr_c; \ + `INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp) diff --git a/verif/env/corev-dv/cva6_instr_gen_config.sv b/verif/env/corev-dv/cva6_instr_gen_config.sv index 05aab13db..510baf529 100644 --- a/verif/env/corev-dv/cva6_instr_gen_config.sv +++ b/verif/env/corev-dv/cva6_instr_gen_config.sv @@ -30,6 +30,7 @@ class cva6_instr_gen_config_c extends riscv_instr_gen_config; bit enable_rdrs1_hazard; bit enable_rdrs2_hazard; bit enable_same_reg; + bit enable_zicond_extension; constraint hazard_reg_c { if (enable_same_reg) { @@ -43,6 +44,7 @@ class cva6_instr_gen_config_c extends riscv_instr_gen_config; `uvm_field_int(enable_rdrs1_hazard, UVM_DEFAULT) `uvm_field_int(enable_rdrs2_hazard, UVM_DEFAULT) `uvm_field_int(enable_same_reg, UVM_DEFAULT) + `uvm_field_int(enable_zicond_extension, UVM_DEFAULT) `uvm_object_utils_end function new (string name = ""); @@ -51,6 +53,7 @@ class cva6_instr_gen_config_c extends riscv_instr_gen_config; get_bool_arg_value("+enable_rdrs1_hazard=", enable_rdrs1_hazard); get_bool_arg_value("+enable_rdrs2_hazard=", enable_rdrs2_hazard); get_bool_arg_value("+enable_same_reg=", enable_same_reg); + get_bool_arg_value("+enable_zicond_extension=", enable_zicond_extension); endfunction endclass : cva6_instr_gen_config_c diff --git a/verif/env/corev-dv/cva6_instr_test_pkg.sv b/verif/env/corev-dv/cva6_instr_test_pkg.sv index 601922656..d09df5765 100644 --- a/verif/env/corev-dv/cva6_instr_test_pkg.sv +++ b/verif/env/corev-dv/cva6_instr_test_pkg.sv @@ -23,6 +23,8 @@ package cva6_instr_test_pkg; `include "cva6_instr_base_test.sv" `include "cva6_instr_hazard_test.sv" `include "cvxif_custom_instr.sv" + `include "riscv_zicond_instr.sv" `include "rv32x_instr.sv" + `include "rv32zicond_instr.sv" endpackage : cva6_instr_test_pkg; diff --git a/verif/env/corev-dv/user_extension/user_define.h b/verif/env/corev-dv/user_extension/user_define.h index e7e3557ff..3a5927485 100644 --- a/verif/env/corev-dv/user_extension/user_define.h +++ b/verif/env/corev-dv/user_extension/user_define.h @@ -1 +1,23 @@ +# Copyright 2023 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# ------------------------------------------------------------------------------ # + # Add user macros, routines in this file + +# Mappings of zicond extension mnemonics to .insn pseudo-op of GAS + + +# CZERO_EQZ rd, rs1, rs2 -> .insn r 0x33, 0x5, 0x7, rd, rs1, rs2 +.macro czero_eqz rd, rs1, rs2 + .insn r 0x33, 0x5, 0x7, \rd, \rs1, \rs2 +.endm + +# CZERO_NEZ rd, rs1, rs2 -> .insn r 0x33, 0x7, 0x7, rd, rs1, rs2 +.macro czero_nez rd, rs1, rs2 + .insn r 0x33, 0x7, 0x7, \rd, \rs1, \rs2 +.endm