diff --git a/src/ariane.sv b/src/ariane.sv index 4afd1d0e7..1914e2835 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -524,18 +524,13 @@ module ariane assign tracer_if.commit_instr = commit_instr_id_commit; assign tracer_if.commit_ack = commit_ack; // address translation - assign tracer_if.lsu_valid = ex_stage_i.lsu_i.lsu_valid_i; - assign tracer_if.vaddr = ex_stage_i.lsu_i.vaddr_i; - // MMU - assign tracer_if.translation_req = ex_stage_i.lsu_i.mmu_i.lsu_req_i; - assign tracer_if.translation_valid = ex_stage_i.lsu_i.mmu_i.lsu_dtlb_hit_o; - assign tracer_if.pte = ex_stage_i.lsu_i.mmu_i.dtlb_content; - assign tracer_if.is_2M = ex_stage_i.lsu_i.mmu_i.dtlb_is_2M; - assign tracer_if.is_1G = ex_stage_i.lsu_i.mmu_i.dtlb_is_1G; - - assign tracer_if.is_store = ex_stage_i.lsu_i.mmu_i.lsu_is_store_i; // was this translation a store - assign tracer_if.st_ready = ex_stage_i.lsu_i.store_unit_i.ready_o; - assign tracer_if.ld_ready = ex_stage_i.lsu_i.load_unit_i.ready_o; + // stores + assign tracer_if.st_valid = ex_stage_i.lsu_i.store_unit_i.store_buffer_i.valid_i; + assign tracer_if.st_paddr = ex_stage_i.lsu_i.store_unit_i.store_buffer_i.paddr_i; + // loads + assign tracer_if.ld_valid = ex_stage_i.lsu_i.load_unit_i.tag_valid_o; + assign tracer_if.ld_kill = ex_stage_i.lsu_i.load_unit_i.kill_req_o; + assign tracer_if.ld_paddr = ex_stage_i.lsu_i.load_unit_i.paddr_i; // exceptions assign tracer_if.exception = commit_stage_i.exception_o; diff --git a/src/load_unit.sv b/src/load_unit.sv index 0d3fbad16..e2ffc76e9 100644 --- a/src/load_unit.sv +++ b/src/load_unit.sv @@ -176,6 +176,7 @@ module load_unit ( // we know for sure that the tag we want to send is valid SEND_TAG: begin tag_valid_o = 1'b1; + NS = IDLE; // we can make a new request here if we got one if (valid_i) begin // start the translation process even though we do not know if the addresses match @@ -208,7 +209,6 @@ module load_unit ( // if we got an exception we need to kill the request immediately if (ex_i.valid) begin kill_req_o = 1'b1; - NS = IDLE; end end diff --git a/src/util/instruction_trace_item.svh b/src/util/instruction_trace_item.svh index decf619bb..48fba7cb0 100755 --- a/src/util/instruction_trace_item.svh +++ b/src/util/instruction_trace_item.svh @@ -198,7 +198,11 @@ class instruction_trace_item; end casex (instr) // check of the instrction was a load or store - INSTR_LOAD, INSTR_STORE: begin + INSTR_STORE: begin + logic [63:0] vaddress = reg_file[read_regs[1]] + this.imm; + s = $sformatf("%s VA: %x PA: %x", s, vaddress, this.paddr); + end + INSTR_LOAD: begin logic [63:0] vaddress = reg_file[read_regs[0]] + this.imm; s = $sformatf("%s VA: %x PA: %x", s, vaddress, this.paddr); end @@ -305,8 +309,8 @@ class instruction_trace_item; default: return printMnemonic("INVALID"); endcase - read_regs.push_back(sbe.rs1); result_regs.push_back(sbe.rd); + read_regs.push_back(sbe.rs1); // save the immediate for calculating the virtual address this.imm = sbe.result; @@ -324,8 +328,8 @@ class instruction_trace_item; default: return printMnemonic("INVALID"); endcase - read_regs.push_back(sbe.rs1); read_regs.push_back(sbe.rs2); + read_regs.push_back(sbe.rs1); // save the immediate for calculating the virtual address this.imm = sbe.result; diff --git a/src/util/instruction_tracer.svh b/src/util/instruction_tracer.svh index 589c5c967..798665557 100755 --- a/src/util/instruction_tracer.svh +++ b/src/util/instruction_tracer.svh @@ -87,7 +87,13 @@ class instruction_tracer; // -------------------- // Address Translation // -------------------- + if (tracer_if.pck.st_valid) begin + store_mapping.push_back(tracer_if.pck.st_paddr); + end + if (tracer_if.pck.ld_valid && !tracer_if.pck.ld_kill) begin + load_mapping.push_back(tracer_if.pck.ld_paddr); + end // -------------- // Commit // -------------- diff --git a/src/util/instruction_tracer_if.sv b/src/util/instruction_tracer_if.sv index b50e732c1..b42d8ac3a 100755 --- a/src/util/instruction_tracer_if.sv +++ b/src/util/instruction_tracer_if.sv @@ -39,25 +39,23 @@ interface instruction_tracer_if ( // commit stage scoreboard_entry commit_instr; // commit instruction logic commit_ack; + // address translation - logic lsu_valid; - // mmu - logic translation_valid; - logic translation_req; - logic [63:0] vaddr; - pte_t pte; - logic is_2M; - logic is_1G; - // lsu - logic is_store; - logic st_ready; - logic ld_ready; + // stores + logic st_valid; + logic [63:0] st_paddr; + // loads + logic ld_valid; + logic ld_kill; + logic [63:0] ld_paddr; + // exceptions exception exception; // the tracer just has a passive interface we do not drive anything with it clocking pck @(posedge clk); - input rstn, flush_unissued, flush, fetch, fetch_valid, fetch_ack, issue_ack, issue_sbe, waddr, lsu_valid, pte, is_2M, is_1G, - wdata, we, commit_instr, commit_ack, translation_valid, vaddr, is_store, st_ready, ld_ready, exception, translation_req; + input rstn, flush_unissued, flush, fetch, fetch_valid, fetch_ack, issue_ack, issue_sbe, waddr, + st_valid, st_paddr, ld_valid, ld_kill, ld_paddr, + wdata, we, commit_instr, commit_ack, exception; endclocking endinterface