diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 61b1148bd..0a6d4c883 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -525,7 +525,6 @@ code_coverage-report:
     - make -C verif/sim generate_cov_dash
     - mv verif/sim/urgReport artifacts/cov_reports/
     - python3 .gitlab-ci/scripts/report_coverage.py artifacts/cov_reports/urgReport/hierarchy.txt
-    - python3 .gitlab-ci/scripts/report_functional_coverage.py artifacts/cov_reports/urgReport/"feature.CVA6 Verification Master Plan1.7.-1268999905.txt"
 
 check gitlab jobs status:
   stage: find failures
diff --git a/.gitlab-ci/scripts/report_functional_coverage.py b/.gitlab-ci/scripts/report_functional_coverage.py
deleted file mode 100644
index b81d47111..000000000
--- a/.gitlab-ci/scripts/report_functional_coverage.py
+++ /dev/null
@@ -1,47 +0,0 @@
-# Copyright 2024 Thales Silicon Security
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com)
-
-import re
-import sys
-import yaml
-import report_builder as rb
-from pprint import pprint
-
-log_path = str(sys.argv[1])
-with open(log_path, 'r') as f:
-    log = f.read()
-
-pattern = re.compile(r'\S{2,}')
-
-def get_scores(component):
-	for l in log.splitlines():
-		if re.search(r'\b'+component+r'\b', l):
-			line = l
-	scores = pattern.findall(line)
-	return [float(scores[0])]
-
-components = [
-	"ISA",
-	"CSR access",
-	"TRAPs",
-]
-
-score_metric = rb.TableMetric('Coverage results')
-score_metric.add_value("FEATURE", "SCORE")
-for component in components:
-	scores = get_scores(component)
-	score_metric.add_value(component, *scores)
-
-report = rb.Report("Functional coverage")
-report.add_metric(score_metric)
-
-report.dump()
-
-for i in range(0, 4):
-	pprint(score_metric.values[i])
diff --git a/verif/sim/cva6.hvp b/verif/sim/cva6.hvp
index d74e50237..b798c5fce 100644
--- a/verif/sim/cva6.hvp
+++ b/verif/sim/cva6.hvp
@@ -725,6 +725,11 @@ plan "CVA6 Verification Master Plan";
         endfeature
         feature "CSR access";
             description = "CSR registers access.\nSpecification: Done, Dvplan: Done, Verification execution: Done";
+            feature "CSR CODE COVERAGE";
+                measure Line, Cond, Toggle CSR_code_cov;
+                    source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.csr_regfile_i";
+                endmeasure
+            endfeature
             feature CYCLE;
                 measure Group CYCLE;
                     source = "group instance: uvme_cva6_pkg.csr_reg_cov.cycle.cycle__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.cycle.cycle__write_cg";