diff --git a/src/mmu.sv b/src/mmu.sv
index b547058ed..86c8b7704 100644
--- a/src/mmu.sv
+++ b/src/mmu.sv
@@ -1,8 +1,8 @@
-// Author: Florian Zaruba, ETH Zurich / David Schaffenrath, TU Graz
+// Author: Florian Zaruba, ETH Zurich
 // Date: 19/04/2017
 // Description: Memory Management Unit for Ariane, contains TLB and
 //              address translation unit. SV39 as defined in RISC-V
-//              privilege specification 1.9
+//              privilege specification 1.11-WIP
 //
 // Copyright (C) 2017 ETH Zurich, University of Bologna
 // All rights reserved.
diff --git a/src/ptw.sv b/src/ptw.sv
index 4c9535427..84f7d659f 100644
--- a/src/ptw.sv
+++ b/src/ptw.sv
@@ -1,8 +1,8 @@
-// Author: David Schaffenrath, TU Graz - Florian Zaruba, ETH Zurich
+// Author: Florian Zaruba, ETH Zurich
+// Author: David Schaffenrath, TU Graz
 // Date: 24.4.2017
 // Description: Hardware-PTW
 //
-//
 // Copyright (C) 2017 ETH Zurich, University of Bologna
 // All rights reserved.
 //
@@ -310,7 +310,7 @@ module ptw #(
         // -------
         // should we have flushed before we got an rvalid, wait for it until going back to IDLE
         if (flush_i) begin
-            // check if we are walking a store, if not than go back to IDLE because
+            // check if we are walking a store, if not then go back to IDLE because
             // all other operations are speculative
             if ((CS == WAIT_GRANT) && data_gnt_i)
                 NS = WAIT_RVALID;
diff --git a/src/tlb.sv b/src/tlb.sv
index 4fecfda01..0262da35e 100644
--- a/src/tlb.sv
+++ b/src/tlb.sv
@@ -1,4 +1,5 @@
-// Author: David Schaffenrath, TU Graz - Florian Zaruba, ETH Zurich
+// Author: David Schaffenrath, TU Graz
+// Author: Florian Zaruba, ETH Zurich
 // Date: 21.4.2017
 // Description: Transaction Lookaside Buffer, SV39
 //              fully set-associative
@@ -21,7 +22,7 @@ import ariane_pkg::*;
 
 module tlb #(
       parameter int unsigned TLB_ENTRIES = 4,
-      parameter int unsigned ASID_WIDTH = 1
+      parameter int unsigned ASID_WIDTH  = 1
   )
   (
     input logic                     clk_i,    // Clock
diff --git a/tb/core_tb.sv b/tb/core_tb.sv
index 16323e176..fe6fab0ad 100644
--- a/tb/core_tb.sv
+++ b/tb/core_tb.sv
@@ -5,6 +5,18 @@
 //
 // Copyright (C) 2017 ETH Zurich, University of Bologna
 // All rights reserved.
+//
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+//
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+//
 
 import ariane_pkg::*;