diff --git a/docs/conf.py b/docs/conf.py index b9d7089e8..36ab7ca52 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -37,7 +37,8 @@ templates_path = ['_templates'] # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. -exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store'] +exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', '*.yaml', '*.xml', +'csr-ip-xact/**/cva6_csr.rst'] # -- Options for HTML output ------------------------------------------------- diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.md b/docs/csr-from-ip-xact/CV32A60X/cva6_csr.md similarity index 100% rename from docs/01_cva6_user/ip-xact/cva6_csr.md rename to docs/csr-from-ip-xact/CV32A60X/cva6_csr.md diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.rst b/docs/csr-from-ip-xact/CV32A60X/cva6_csr.rst similarity index 100% rename from docs/01_cva6_user/ip-xact/cva6_csr.rst rename to docs/csr-from-ip-xact/CV32A60X/cva6_csr.rst diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.xml b/docs/csr-from-ip-xact/CV32A60X/cva6_csr.xml similarity index 100% rename from docs/01_cva6_user/ip-xact/cva6_csr.xml rename to docs/csr-from-ip-xact/CV32A60X/cva6_csr.xml diff --git a/docs/01_cva6_user/ip-xact/cva6_csr.yaml b/docs/csr-from-ip-xact/CV32A60X/cva6_csr.yaml similarity index 100% rename from docs/01_cva6_user/ip-xact/cva6_csr.yaml rename to docs/csr-from-ip-xact/CV32A60X/cva6_csr.yaml diff --git a/docs/csr-from-ip-xact/embedded/cva6_csr.md b/docs/csr-from-ip-xact/embedded/cva6_csr.md new file mode 100644 index 000000000..8d62a11c4 --- /dev/null +++ b/docs/csr-from-ip-xact/embedded/cva6_csr.md @@ -0,0 +1,1146 @@ + + +# CSR REGISTERS : CV32A6 +### Unimplemented CSR accessing generates an illegal instruction exception. +### Read-Only CSR write access generates an illegal instruction exception. + +## MSTATUS : Machine Status Register +### *AddressOffset*: 'h300 +### *Description*: +The ``mstatus`` register keeps track of and controls the hart’s current operating state. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31 | SD | State dirty | 0x0 | read-only,WARL | The SD bit is a read\-only bit\.``Legal Values``:0\. // ``Enumerated Values``( "Not_Dirty" :0 ) ( "Dirty" :1 ) | +| 30:23 | reserved_0 | Reserved | 0x0 | read-write,WPRI | Reserved| +| 22 | TSR | Trap sret | 0x0 | read-write,WARL | The TSR bit supports intercepting the supervisor exception return instruction, SRET\. // ``Enumerated Values``( "Permitted" :0 ) ( "Not_Permitted" :1 ) | +| 21 | TW | Timeout wait | 0x0 | read-write,WARL | The TW bit supports intercepting the WFI instruction\. // ``Enumerated Values``( "Permitted" :0 ) ( "Not_Permitted" :1 ) | +| 20 | TVM | Trap virtual memory | 0x0 | read-write,WARL | The TVM bit supports intercepting supervisor virtual\-memory management operations\. // ``Enumerated Values``( "Permitted" :0 ) ( "Not_Permitted" :1 ) | +| 19 | MXR | Make executable readable | 0x0 | read-write | The MXR bit modifies the privilege with which loads access virtual memory\. // ``Enumerated Values``( "Not_Executable" :0 ) ( "Executable" :1 ) | +| 18 | SUM | Supervisor user memory | 0x0 | read-write | The SUM bit modifies the privilege with which S\-mode loads and stores access virtual memory\. // ``Enumerated Values``( "Not_Permitted" :0 ) ( "Permitted" :1 ) | +| 17 | MPRV | Modify privilege | 0x0 | read-write | The MPRV bit modifies the privilege mode at which loads and stores execute\. // ``Enumerated Values``( "Normal" :0 ) ( "Protected" :1 ) | +| 16:15 | XS | Extension state | 0x0 | read-only,WARL | The XS field encodes the status of the additional user\-mode extensions and associated state\.``Legal Values``:0\. // ``Enumerated Values``( "Off" :0 ) ( "Initial" :1 ) ( "Clean" :2 ) ( "Dirty" :3 ) | +| 14:13 | FS | Floating-point unit state | 0x0 | read-only,WARL | FS extension is not supported\.``Legal Values``:0\. // ``Enumerated Values``( "Off" :0 ) ( "Initial" :1 ) ( "Clean" :2 ) ( "Dirty" :3 ) | +| 12:11 | MPP | Machine mode prior privilege | 0x0 | read-write | Holds the previous privilege mode for machine mode\. // ``Enumerated Values``( "U-mode" :0 ) ( "S-mode" :1 ) ( "Reserved" :2 ) ( "M-mode" :3 ) | +| 10:9 | VS | Vector extension state | 0x0 | read-only,WARL | V extension is not supported\.``Legal Values``:0\.| +| 8 | SPP | Supervisor mode prior privilege | 0x0 | read-write | Holds the previous privilege mode for supervisor mode\. // ``Enumerated Values``( "U-mode" :0 ) ( "Otherwise" :1 ) | +| 7 | MPIE | Machine mode prior interrupt enable | 0x0 | read-write | Indicates whether machine interrupts were enabled prior to trapping into machine mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | +| 6 | UBE | User mode bit endianess | 0x0 | read-write,WARL | UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | +| 5 | SPIE | Supervisor mode prior interrupt enable | 0x0 | read-write | Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | +| 4 | reserved_1 | Reserved | 0x0 | read-write,WPRI | Reserved| +| 3 | MIE | Machine mode interrupt enable | 0x0 | read-write | Global interrupt\-enable bit for Machine mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | +| 2 | reserved_2 | Reserved | 0x0 | read-write,WPRI | Reserved| +| 1 | SIE | Supervisor mode interrupt enable | 0x0 | read-write | Global interrupt\-enable bit for Supervisor mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | +| 0 | reserved_3 | Reserved | 0x0 | read-write,WPRI | Reserved| + +## MISA : Machine ISA Register +### *AddressOffset*: 'h301 +### *Description*: +The misa CSR is reporting the ISA supported by the hart. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:30 | MXL | Machine xlen | 0x0 | read-write,WARL | The MXL field encodes the native base integer ISA width\.``Legal Values``:1\. // ``Enumerated Values``( "XLEN_32" :1 ) ( "XLEN_64" :2 ) ( "XLEN_128" :3 ) | +| 29:26 | Reserved_26 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 25:0 | Extensions | Extensions | 0x141104 | read-write,WARL | The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet\.``Legal Values``:0x141104\. // ``Enumerated Values``( "A" :1 ) ( "B" :2 ) ( "C" :4 ) ( "D" :8 ) ( "E" :16 ) ( "F" :32 ) ( "G" :64 ) ( "H" :128 ) ( "I" :256 ) ( "J" :512 ) ( "K" :1024 ) ( "L" :2048 ) ( "M" :4096 ) ( "N" :8192 ) ( "O" :16384 ) ( "P" :32768 ) ( "Q" :65536 ) ( "R" :131072 ) ( "S" :262144 ) ( "T" :524288 ) ( "U" :1048576 ) ( "V" :2097152 ) ( "W" :4194304 ) ( "X" :8388608 ) ( "Y" :16777216 ) ( "Z" :33554432 ) | + +## MIE : Machine Interrupt Enable Register +### *AddressOffset*: 'h304 +### *Description*: +This register contains machine interrupt enable bits. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 15:12 | Reserved_12 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 11 | MEIE | M-mode external interrupt enable | 0x0 | read-write,WARL | Enables machine mode external interrupts\.| +| 10 | Reserved_10 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 9 | SEIE | S-mode external interrupt enable | 0x0 | read-write,WARL | Enables supervisor mode external interrupts\.| +| 8 | UEIE | | 0x0 | read-write,WARL | enables U\-mode external interrupts\.``Legal Values:``0\.| +| 7 | MTIE | M-mode timer interrupt enable | 0x0 | read-write,WARL | Enables machine mode timer interrupts\.| +| 6 | Reserved_6 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 5 | STIE | S-mode timer interrupt enable | 0x0 | read-write,WARL | Enables supervisor mode timer interrupts\.| +| 4 | UTIE | | 0x0 | read-write,WARL | timer interrupt\-enable bit for U\-mode\.``Legal Values:``0\.| +| 3 | MSIE | M-mode software interrupt enable | 0x0 | read-write | Enables machine mode software interrupts\.| +| 2 | Reserved_2 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 1 | SSIE | S-mode software interrupt enable | 0x0 | read-write,WARL | Enables supervisor mode software interrupts\.| +| 0 | USIE | | 0x0 | read-write,WARL | enable U\-mode software interrrupts\.``Legal Values:``0\.| + +## MTVEC : Machine Trap Vector Register +### *AddressOffset*: 'h305 +### *Description*: +This register holds trap vector configuration, consisting of a vector base address and a vector mode. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:2 | BASE | | 0x0 | read-write,WARL | The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4\-byte aligned, and when MODE=Vectored the address must be 256\-byte aligned\.| +| 1:0 | MODE | | 0x0 | read-write,WARL | Imposes additional alignment constraints on the value in the BASE field\.``Legal Values :``0,1\. // ``Enumerated Values``( "Direct" :0 ) ( "Vectored" :1 ) ( "Reserved_2" :2 ) ( "Reserved_3" :3 ) | + +## MSTATUSH : Upper 32-bits of Machine Status Register +### *AddressOffset*: 'h310 +### *Description*: +The ``mstatush`` is the upper 32-bits of Machine status only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 3:0 | reserved_0 | Reserved | 0x0 | read-write,WPRI | Reserved| +| 4 | SBE | Supervisor mode bit endianess | 0x0 | read-write,WARL | SBE controls whether explicit load and store memory accesses made from S\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | +| 5 | MBE | Machine mode bit endianess | 0x0 | read-write,WARL | MBE controls whether explicit load and store memory accesses made from M\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | +| 31:6 | reserved_1 | Reserved | 0x0 | read-write,WPRI | Reserved| + +## MHPMEVENT3 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h323 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT4 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h324 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT5 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h325 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT6 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h326 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT7 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h327 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT8 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h328 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT9 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h329 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT10 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h32a +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT11 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h32b +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT12 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h32c +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT13 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h32d +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT14 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h32e +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT15 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h32f +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT16 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h330 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT17 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h331 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT18 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h332 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT19 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h333 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT20 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h334 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT21 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h335 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT22 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h336 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT23 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h337 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT24 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h338 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT25 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h339 +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT26 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h33a +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT27 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h33b +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT28 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h33c +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT29 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h33d +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT30 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h33e +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MHPMEVENT31 : Machine Hardware Performance-Monitoring Event Selector Register +### *AddressOffset*: 'h33f +### *Description*: +This register controls which event causes the corresponding counter to increment. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mhpmevent | | 0x0 | WARL | Event selector CSRs\.``Legal Values``:0\.| + +## MSCRATCH : Machine Scratch Register +### *AddressOffset*: 'h340 +### *Description*: +This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mscratch | Machine scratch | 0x0 | read-write | Holds a value dedicated to Machine mode\.| + +## MEPC : Machine Exception Program Counter Register +### *AddressOffset*: 'h341 +### *Description*: +This register must be able to hold all valid virtual addresses. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mepc | Machine exception program counter | 0x0 | read-write,WARL | When a trap is taken into M\-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception\.| + +## MCAUSE : Machine Cause Register +### *AddressOffset*: 'h342 +### *Description*: +When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. +Machine cause register (``mcause``) values after trap are shown in the following table. +|Interrupt|Exception Code|Description| +|---------|--------------|-----------| +|1|0|*Reserved*| +|1|1|Supervisor software interrupt| +|1|2-4|*Reserved*| +|1|5|Supervisor timer interrupt| +|1|6-8|*Reserved*| +|1|9|Supervisor external interrupt| +|1|10-15|*Reserved*| +|1|≥16|*Designated for platform use*| +|0|0|Instruction address misaligned| +|0|1|Instruction access fault| +|0|2|Illegal instruction| +|0|3|Breakpoint| +|0|4|Load address misaligned| +|0|5|Load access fault| +|0|6|Store/AMO address misaligned| +|0|7|Store/AMO access fault| +|0|8|Environment call from U-mode| +|0|9|Environment call from S-mode| +|0|10-11|*Reserved*| +|0|12|Instruction page fault| +|0|13|Load page fault| +|0|14|*Reserved*| +|0|15|Store/AMO page fault| +|0|16-23|*Reserved*| +|0|24-31|*Designated for custom use*| +|0|32-47|*Reserved*| +|0|48-63|*Designated for custom use*| +|0|≥64|*Reserved*| + +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31 | Interrupt | Interrupt | 0x0 | read-write | This bit is set if the trap was caused by an interrupt\.| +| 30:0 | exception_code | Exception code | 0x0 | read-write,WLRL | This field contains a code identifying the last exception or interrupt\.| + +## MTVAL : Machine Trap Value Register +### *AddressOffset*: 'h343 +### *Description*: +When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | mtval | Machine trap value | 0x0 | read-write,WARL | If ``mtval`` is written with a nonzero value when a breakpoint, address\-misaligned, access\-fault, or page\-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address\. If ``mtval`` is written with a nonzero value when a misaligned load or store causes an access\-fault or page\-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault\. If ``mtval`` is written with a nonzero value when an instruction access\-fault or page\-fault exception occurs on a system with variable\-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction\.| + +## MIP : Machine Interrupt Pending Register +### *AddressOffset*: 'h344 +### *Description*: +This register contains machine interrupt pending bits. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 15:12 | Reserved_12 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 11 | MEIP | M-mode external interrupt pending | 0x0 | read-only | The interrupt\-pending bit for machine\-level external interrupts\.| +| 10 | Reserved_10 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 9 | SEIP | S-mode external interrupt pending | 0x0 | read-write | The interrupt\-pending bit for supervisor\-level external interrupts\.| +| 8 | UEIP | | 0x0 | read-write | enables external interrupts\.``Legal Values:``0\.| +| 7 | MTIP | M-mode timer interrupt pending | 0x0 | read-only | The interrupt\-pending bit for machine\-level timer interrupts\.| +| 6 | Reserved_6 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 5 | STIP | S-mode timer interrupt pending | 0x0 | read-write | The interrupt\-pending bit for supervisor\-level timer interrupts\.| +| 4 | UTIP | | 0x0 | read-write | Correspond to timer interrupt\-pending bits for user interrupt\.``Legal Values:``0\.| +| 3 | MSIP | M-mode software interrupt pending | 0x0 | read-only | The interrupt\-pending bit for machine\-level software interrupts\.| +| 2 | Reserved_2 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| +| 1 | SSIP | S-mode software interrupt pending | 0x0 | read-write | The interrupt\-pending bit for supervisor\-level software interrupts\.| +| 0 | USIP | | 0x0 | read-write | A hart to directly write its own USIP bits when running in the appropriate mode\.``Legal Values:``0\.| + +## PMPCFG0 : Physical Memory Protection Config 0 Register +### *AddressOffset*: 'h3a0 +### *Description*: +Holds configuration 0-3. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:24 | pmp3cfg | Physical memory protection 3 config | 0x0 | read-write | Holds the configuration\.| +| 23:16 | pmp2cfg | Physical memory protection 2 config | 0x0 | read-write | Holds the configuration\.| +| 15:8 | pmp1cfg | Physical memory protection 1 config | 0x0 | read-write | Holds the configuration\.| +| 7:0 | pmp0cfg | Physical memory protection 0 config | 0x0 | read-write | Holds the configuration\.| + +## PMPCFG1 : Physical Memory Protection Config 1 Register +### *AddressOffset*: 'h3a1 +### *Description*: +Holds configuration 4-7. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:24 | pmp7cfg | Physical memory protection 7 config | 0x0 | read-write | Holds the configuration\.| +| 23:16 | pmp6cfg | Physical memory protection 6 config | 0x0 | read-write | Holds the configuration\.| +| 15:8 | pmp5cfg | Physical memory protection 5 config | 0x0 | read-write | Holds the configuration\.| +| 7:0 | pmp4cfg | Physical memory protection 4 config | 0x0 | read-write | Holds the configuration\.| + +## PMPCFG2 : Physical Memory Protection Config 2 Register +### *AddressOffset*: 'h3a2 +### *Description*: +Holds configuration 8-11. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:24 | pmp11cfg | Physical memory protection 11 config | 0x0 | read-write | Holds the configuration\.| +| 23:16 | pmp10cfg | Physical memory protection 10 config | 0x0 | read-write | Holds the configuration\.| +| 15:8 | pmp9cfg | Physical memory protection 9 config | 0x0 | read-write | Holds the configuration\.| +| 7:0 | pmp8cfg | Physical memory protection 8 config | 0x0 | read-write | Holds the configuration\.| + +## PMPCFG3 : Physical Memory Protection Config 3 Register +### *AddressOffset*: 'h3a3 +### *Description*: +Holds configuration 12-15. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:24 | pmp15cfg | Physical memory protection 15 config | 0x0 | read-write | Holds the configuration\.| +| 23:16 | pmp14cfg | Physical memory protection 14 config | 0x0 | read-write | Holds the configuration\.| +| 15:8 | pmp13cfg | Physical memory protection 13 config | 0x0 | read-write | Holds the configuration\.| +| 7:0 | pmp12cfg | Physical memory protection 12 config | 0x0 | read-write | Holds the configuration\.| + +## PMPADDR0 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b0 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR1 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b1 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR2 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b2 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR3 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b3 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR4 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b4 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR5 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b5 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR6 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b6 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR7 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b7 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR8 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b8 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR9 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3b9 +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR10 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3ba +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR11 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3bb +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR12 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3bc +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR13 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3bd +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR14 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3be +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## PMPADDR15 : Physical Memory Protection Address Register +### *AddressOffset*: 'h3bf +### *Description*: +Address register for Physical Memory Protection. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | address | Address | 0x0 | read-write,WARL | Encodes bits 33\-2 of a 34\-bit physical address\.| + +## ICACHE : Instruction Cache Register +### *AddressOffset*: 'h7C0 +### *Description*: +Custom Register to enable/disable for Icache [bit 0] +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:1 | reserved_0 | Reserved | 0x0 | read-only | Reserved| +| 0 | icache | Instruction cache | 0x1 | read-write | Custom Register| + +## MCYCLE : M-mode Cycle counter Register +### *AddressOffset*: 'hB00 +### *Description*: +Counts the number of clock cycles executed by the processor core on which the hart is running. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-write | Counts the number of clock cycles executed by the processor core\.| + +## MINSTRET : Machine Instruction Retired counter Register +### *AddressOffset*: 'hB02 +### *Description*: +Counts the number of instructions the hart has retired. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-write | Counts the number of instructions the hart has retired\.| + +## MCYCLEH : Upper 32-bits of M-mode Cycle counter Register +### *AddressOffset*: 'hB80 +### *Description*: +Counts the number of clock cycles executed by the processor core on which the hart is running. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-write | Counts the number of clock cycles executed by the processor core\.| + +## MINSTRETH : Upper 32-bits of Machine Instruction Retired counter Register +### *AddressOffset*: 'hB82 +### *Description*: +Counts the number of instructions the hart has retired. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-write | Counts the number of instructions the hart has retired\.| + +## MHPMCOUNTER3 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb03 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER4 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb04 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER5 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb05 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER6 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb06 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER7 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb07 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER8 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb08 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER9 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb09 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER10 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb0a +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER11 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb0b +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER12 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb0c +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER13 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb0d +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER14 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb0e +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER15 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb0f +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER16 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb10 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER17 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb11 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER18 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb12 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER19 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb13 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER20 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb14 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER21 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb15 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER22 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb16 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER23 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb17 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER24 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb18 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER25 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb19 +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER26 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb1a +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER27 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb1b +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER28 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb1c +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER29 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb1d +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER30 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb1e +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTER31 : Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb1f +### *Description*: +Hardware performance event counter. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH3 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb83 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH4 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb84 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH5 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb85 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH6 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb86 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH7 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb87 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH8 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb88 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH9 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb89 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH10 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb8a +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH11 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb8b +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH12 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb8c +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH13 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb8d +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH14 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb8e +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH15 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb8f +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH16 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb90 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH17 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb91 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH18 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb92 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH19 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb93 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH20 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb94 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH21 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb95 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH22 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb96 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH23 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb97 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH24 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb98 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH25 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb99 +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH26 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb9a +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH27 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb9b +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH28 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb9c +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH29 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb9d +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH30 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb9e +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## MHPMCOUNTERH31 : Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +### *AddressOffset*: 'hb9f +### *Description*: +Hardware performance event counter only for RV32. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | WARL | ``Legal Values``: 0\.| + +## CYCLE : Cycle counter Register +### *AddressOffset*: 'hC00 +### *Description*: +Cycle counter for RDCYCLE instruction. Shadow of mcycle. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-only | Count| + +## INSTRET : Instruction Retired counter Register +### *AddressOffset*: 'hC02 +### *Description*: +Instructions-retired counter for RDINSTRET instruction. Shadow of minstret. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-only | Count| + +## CYCLEH : Upper 32-bits of Cycle counter Register +### *AddressOffset*: 'hC80 +### *Description*: +Cycle counter for RDCYCLE instruction. Shadow of mcycleh. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-only | Count| + +## INSTRETH : Upper 32-bits of Instruction Retired counter Register +### *AddressOffset*: 'hC82 +### *Description*: +Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | count | Count | 0x0 | read-only | Count| + +## MVENDORID : Machine Vendor ID Register +### *AddressOffset*: 'hF11 +### *Description*: +This register provids the JEDEC manufacturer ID of the provider of the core. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:7 | bank | Bank | 0xC0 | read-only | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.| +| 6:0 | offset | Offset | 0x20 | read-only | Contain encording for the final byte discarding the parity bit\.| + +## MARCHID : Machine Architecture ID Register +### *AddressOffset*: 'hF12 +### *Description*: +This register encodes the base microarchitecture of the hart. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | architecture_id | Architecture id | 0x3 | read-only | Provide Encoding the base microarchitecture of the hart\.| + +## MIMPID : Machine Implementation ID Register +### *AddressOffset*: 'hF13 +### *Description*: +Provides a unique encoding of the version of the processor implementation. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | implementation | Implementation | 0x0 | read-only | Provides unique encoding of the version of the processor implementation\.| + +## MHARTID : Machine Hardware Thread ID Register +### *AddressOffset*: 'hF14 +### *Description*: +This register contains the integer ID of the hardware thread running the code. +| BIT | NAME | displayName |Reset| RIGHT | Description | +| --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | +| 31:0 | hart_id | Hart id | 0x0 | read-only | Contains the integer ID of the hardware thread running the code\.| diff --git a/docs/csr-from-ip-xact/embedded/cva6_csr.rst b/docs/csr-from-ip-xact/embedded/cva6_csr.rst new file mode 100644 index 000000000..257fabbee --- /dev/null +++ b/docs/csr-from-ip-xact/embedded/cva6_csr.rst @@ -0,0 +1,3747 @@ +.. code-block:: none + + Copyright (c) 2023 Thales Silicon Security + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + Author: Mohamed Aziz FRIKHA + + +REGISTERS CSR CV32A6 +=================== +Unimplemented CSR accessing generates an illegal instruction exception. +-------------------------- +Read-Only CSR write access generates an illegal instruction exception. +-------------------------- + +MSTATUS:Machine Status Register +-------------------------- +AddressOffset: 'h300 +-------------------------- +Description: +-------------------------- +The ``mstatus`` register keeps track of and controls the hart’s current operating state. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31 + - SD + - State dirty + - 0x0 + - read-only,WARL + - The SD bit is a read\-only bit\.``Legal Values``:0\. ``Enumerated Values``( "Not_Dirty" :0)( "Dirty" :1)'\n' + * - 30:23 + - reserved_0 + - Reserved + - 0x0 + - read-write,WPRI + - Reserved + * - 22 + - TSR + - Trap sret + - 0x0 + - read-write,WARL + - The TSR bit supports intercepting the supervisor exception return instruction, SRET\. ``Enumerated Values``( "Permitted" :0)( "Not_Permitted" :1)'\n' + * - 21 + - TW + - Timeout wait + - 0x0 + - read-write,WARL + - The TW bit supports intercepting the WFI instruction\. ``Enumerated Values``( "Permitted" :0)( "Not_Permitted" :1)'\n' + * - 20 + - TVM + - Trap virtual memory + - 0x0 + - read-write,WARL + - The TVM bit supports intercepting supervisor virtual\-memory management operations\. ``Enumerated Values``( "Permitted" :0)( "Not_Permitted" :1)'\n' + * - 19 + - MXR + - Make executable readable + - 0x0 + - read-write + - The MXR bit modifies the privilege with which loads access virtual memory\. ``Enumerated Values``( "Not_Executable" :0)( "Executable" :1)'\n' + * - 18 + - SUM + - Supervisor user memory + - 0x0 + - read-write + - The SUM bit modifies the privilege with which S\-mode loads and stores access virtual memory\. ``Enumerated Values``( "Not_Permitted" :0)( "Permitted" :1)'\n' + * - 17 + - MPRV + - Modify privilege + - 0x0 + - read-write + - The MPRV bit modifies the privilege mode at which loads and stores execute\. ``Enumerated Values``( "Normal" :0)( "Protected" :1)'\n' + * - 16:15 + - XS + - Extension state + - 0x0 + - read-only,WARL + - The XS field encodes the status of the additional user\-mode extensions and associated state\.``Legal Values``:0\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 14:13 + - FS + - Floating-point unit state + - 0x0 + - read-only,WARL + - FS extension is not supported\.``Legal Values``:0\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 12:11 + - MPP + - Machine mode prior privilege + - 0x0 + - read-write + - Holds the previous privilege mode for machine mode\. ``Enumerated Values``( "U-mode" :0)( "S-mode" :1)( "Reserved" :2)( "M-mode" :3)'\n' + * - 10:9 + - VS + - Vector extension state + - 0x0 + - read-only,WARL + - V extension is not supported\.``Legal Values``:0\. + * - 8 + - SPP + - Supervisor mode prior privilege + - 0x0 + - read-write + - Holds the previous privilege mode for supervisor mode\. ``Enumerated Values``( "U-mode" :0)( "Otherwise" :1)'\n' + * - 7 + - MPIE + - Machine mode prior interrupt enable + - 0x0 + - read-write + - Indicates whether machine interrupts were enabled prior to trapping into machine mode\. ``Enumerated Values``( "Disabled" :0)( "Enabled" :1)'\n' + * - 6 + - UBE + - User mode bit endianess + - 0x0 + - read-write,WARL + - UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' + * - 5 + - SPIE + - Supervisor mode prior interrupt enable + - 0x0 + - read-write + - Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. ``Enumerated Values``( "Disabled" :0)( "Enabled" :1)'\n' + * - 4 + - reserved_1 + - Reserved + - 0x0 + - read-write,WPRI + - Reserved + * - 3 + - MIE + - Machine mode interrupt enable + - 0x0 + - read-write + - Global interrupt\-enable bit for Machine mode\. ``Enumerated Values``( "Disabled" :0)( "Enabled" :1)'\n' + * - 2 + - reserved_2 + - Reserved + - 0x0 + - read-write,WPRI + - Reserved + * - 1 + - SIE + - Supervisor mode interrupt enable + - 0x0 + - read-write + - Global interrupt\-enable bit for Supervisor mode\. ``Enumerated Values``( "Disabled" :0)( "Enabled" :1)'\n' + * - 0 + - reserved_3 + - Reserved + - 0x0 + - read-write,WPRI + - Reserved + +MISA:Machine ISA Register +-------------------------- +AddressOffset: 'h301 +-------------------------- +Description: +-------------------------- +The misa CSR is reporting the ISA supported by the hart. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:30 + - MXL + - Machine xlen + - 0x0 + - read-write,WARL + - The MXL field encodes the native base integer ISA width\.``Legal Values``:1\. ``Enumerated Values``( "XLEN_32" :1)( "XLEN_64" :2)( "XLEN_128" :3)'\n' + * - 29:26 + - Reserved_26 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 25:0 + - Extensions + - Extensions + - 0x141104 + - read-write,WARL + - The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet\.``Legal Values``:0x141104\. ``Enumerated Values``( "A" :1)( "B" :2)( "C" :4)( "D" :8)( "E" :16)( "F" :32)( "G" :64)( "H" :128)( "I" :256)( "J" :512)( "K" :1024)( "L" :2048)( "M" :4096)( "N" :8192)( "O" :16384)( "P" :32768)( "Q" :65536)( "R" :131072)( "S" :262144)( "T" :524288)( "U" :1048576)( "V" :2097152)( "W" :4194304)( "X" :8388608)( "Y" :16777216)( "Z" :33554432)'\n' + +MIE:Machine Interrupt Enable Register +-------------------------- +AddressOffset: 'h304 +-------------------------- +Description: +-------------------------- +This register contains machine interrupt enable bits. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 15:12 + - Reserved_12 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 11 + - MEIE + - M-mode external interrupt enable + - 0x0 + - read-write,WARL + - Enables machine mode external interrupts\. + * - 10 + - Reserved_10 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 9 + - SEIE + - S-mode external interrupt enable + - 0x0 + - read-write,WARL + - Enables supervisor mode external interrupts\. + * - 8 + - UEIE + - + - 0x0 + - read-write,WARL + - enables U\-mode external interrupts\.``Legal Values:``0\. + * - 7 + - MTIE + - M-mode timer interrupt enable + - 0x0 + - read-write,WARL + - Enables machine mode timer interrupts\. + * - 6 + - Reserved_6 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 5 + - STIE + - S-mode timer interrupt enable + - 0x0 + - read-write,WARL + - Enables supervisor mode timer interrupts\. + * - 4 + - UTIE + - + - 0x0 + - read-write,WARL + - timer interrupt\-enable bit for U\-mode\.``Legal Values:``0\. + * - 3 + - MSIE + - M-mode software interrupt enable + - 0x0 + - read-write + - Enables machine mode software interrupts\. + * - 2 + - Reserved_2 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 1 + - SSIE + - S-mode software interrupt enable + - 0x0 + - read-write,WARL + - Enables supervisor mode software interrupts\. + * - 0 + - USIE + - + - 0x0 + - read-write,WARL + - enable U\-mode software interrrupts\.``Legal Values:``0\. + +MTVEC:Machine Trap Vector Register +-------------------------- +AddressOffset: 'h305 +-------------------------- +Description: +-------------------------- +This register holds trap vector configuration, consisting of a vector base address and a vector mode. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:2 + - BASE + - + - 0x0 + - read-write,WARL + - The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4\-byte aligned, and when MODE=Vectored the address must be 256\-byte aligned\. + * - 1:0 + - MODE + - + - 0x0 + - read-write,WARL + - Imposes additional alignment constraints on the value in the BASE field\.``Legal Values :``0,1\. ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n' + +MSTATUSH:Upper 32-bits of Machine Status Register +-------------------------- +AddressOffset: 'h310 +-------------------------- +Description: +-------------------------- +The ``mstatush`` is the upper 32-bits of Machine status only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 3:0 + - reserved_0 + - Reserved + - 0x0 + - read-write,WPRI + - Reserved + * - 4 + - SBE + - Supervisor mode bit endianess + - 0x0 + - read-write,WARL + - SBE controls whether explicit load and store memory accesses made from S\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' + * - 5 + - MBE + - Machine mode bit endianess + - 0x0 + - read-write,WARL + - MBE controls whether explicit load and store memory accesses made from M\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' + * - 31:6 + - reserved_1 + - Reserved + - 0x0 + - read-write,WPRI + - Reserved + +MHPMEVENT3:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h323 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT4:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h324 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT5:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h325 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT6:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h326 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT7:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h327 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT8:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h328 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT9:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h329 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT10:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h32a +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT11:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h32b +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT12:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h32c +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT13:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h32d +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT14:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h32e +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT15:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h32f +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT16:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h330 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT17:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h331 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT18:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h332 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT19:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h333 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT20:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h334 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT21:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h335 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT22:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h336 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT23:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h337 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT24:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h338 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT25:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h339 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT26:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h33a +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT27:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h33b +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT28:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h33c +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT29:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h33d +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT30:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h33e +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MHPMEVENT31:Machine Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h33f +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mhpmevent + - + - 0x0 + - WARL + - Event selector CSRs\.``Legal Values``:0\. + +MSCRATCH:Machine Scratch Register +-------------------------- +AddressOffset: 'h340 +-------------------------- +Description: +-------------------------- +This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mscratch + - Machine scratch + - 0x0 + - read-write + - Holds a value dedicated to Machine mode\. + +MEPC:Machine Exception Program Counter Register +-------------------------- +AddressOffset: 'h341 +-------------------------- +Description: +-------------------------- +This register must be able to hold all valid virtual addresses. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mepc + - Machine exception program counter + - 0x0 + - read-write,WARL + - When a trap is taken into M\-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception\. + +MCAUSE:Machine Cause Register +-------------------------- +AddressOffset: 'h342 +-------------------------- +Description: +-------------------------- +When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. +Machine cause register (``mcause``) values after trap are shown in the following table. + +.. list-table:: + :widths: 20 20 20 + :header-rows: 1 + + * - **Interrupt** + - **Exception Code** + - **Description** + * - 1 + - 0 + - *Reserved* + * - 1 + - 1 + - Supervisor software interrupt + * - 1 + - 2-4 + - *Reserved* + * - 1 + - 5 + - Supervisor timer interrupt + * - 1 + - 6-8 + - *Reserved* + * - 1 + - 9 + - Supervisor external interrupt + * - 1 + - 10-15 + - *Reserved* + * - 1 + - >=16 + - *Designated for platform use* + * - 0 + - 0 + - Instruction address misaligned + * - 0 + - 1 + - Instruction access fault + * - 0 + - 2 + - Illegal instruction + * - 0 + - 3 + - Breakpoint + * - 0 + - 4 + - Load address misaligned + * - 0 + - 5 + - Load access fault + * - 0 + - 6 + - Store/AMO address misaligned + * - 0 + - 7 + - Store/AMO access fault + * - 0 + - 8 + - Environment call from U-mode + * - 0 + - 9 + - Environment call from S-mode + * - 0 + - 10-11 + - *Reserved* + * - 0 + - 12 + - Instruction page fault + * - 0 + - 13 + - Load page fault + * - 0 + - 14 + - *Reserved* + * - 0 + - 15 + - Store/AMO page fault + * - 0 + - 16-23 + - *Reserved* + * - 0 + - 24-31 + - *Designated for custom use* + * - 0 + - 32-47 + - *Reserved* + * - 0 + - 48-63 + - *Designated for custom use* + * - 0 + - >=64 + - *Reserved* + + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31 + - Interrupt + - Interrupt + - 0x0 + - read-write + - This bit is set if the trap was caused by an interrupt\. + * - 30:0 + - exception_code + - Exception code + - 0x0 + - read-write,WLRL + - This field contains a code identifying the last exception or interrupt\. + +MTVAL:Machine Trap Value Register +-------------------------- +AddressOffset: 'h343 +-------------------------- +Description: +-------------------------- +When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - mtval + - Machine trap value + - 0x0 + - read-write,WARL + - If ``mtval`` is written with a nonzero value when a breakpoint, address\-misaligned, access\-fault, or page\-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address\. If ``mtval`` is written with a nonzero value when a misaligned load or store causes an access\-fault or page\-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault\. If ``mtval`` is written with a nonzero value when an instruction access\-fault or page\-fault exception occurs on a system with variable\-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction\. + +MIP:Machine Interrupt Pending Register +-------------------------- +AddressOffset: 'h344 +-------------------------- +Description: +-------------------------- +This register contains machine interrupt pending bits. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 15:12 + - Reserved_12 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 11 + - MEIP + - M-mode external interrupt pending + - 0x0 + - read-only + - The interrupt\-pending bit for machine\-level external interrupts\. + * - 10 + - Reserved_10 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 9 + - SEIP + - S-mode external interrupt pending + - 0x0 + - read-write + - The interrupt\-pending bit for supervisor\-level external interrupts\. + * - 8 + - UEIP + - + - 0x0 + - read-write + - enables external interrupts\.``Legal Values:``0\. + * - 7 + - MTIP + - M-mode timer interrupt pending + - 0x0 + - read-only + - The interrupt\-pending bit for machine\-level timer interrupts\. + * - 6 + - Reserved_6 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 5 + - STIP + - S-mode timer interrupt pending + - 0x0 + - read-write + - The interrupt\-pending bit for supervisor\-level timer interrupts\. + * - 4 + - UTIP + - + - 0x0 + - read-write + - Correspond to timer interrupt\-pending bits for user interrupt\.``Legal Values:``0\. + * - 3 + - MSIP + - M-mode software interrupt pending + - 0x0 + - read-only + - The interrupt\-pending bit for machine\-level software interrupts\. + * - 2 + - Reserved_2 + - Reserved + - 0x0 + - read-write,WARL + - Reserved\.``Legal Values:``0\. + * - 1 + - SSIP + - S-mode software interrupt pending + - 0x0 + - read-write + - The interrupt\-pending bit for supervisor\-level software interrupts\. + * - 0 + - USIP + - + - 0x0 + - read-write + - A hart to directly write its own USIP bits when running in the appropriate mode\.``Legal Values:``0\. + +PMPCFG0:Physical Memory Protection Config 0 Register +-------------------------- +AddressOffset: 'h3a0 +-------------------------- +Description: +-------------------------- +Holds configuration 0-3. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:24 + - pmp3cfg + - Physical memory protection 3 config + - 0x0 + - read-write + - Holds the configuration\. + * - 23:16 + - pmp2cfg + - Physical memory protection 2 config + - 0x0 + - read-write + - Holds the configuration\. + * - 15:8 + - pmp1cfg + - Physical memory protection 1 config + - 0x0 + - read-write + - Holds the configuration\. + * - 7:0 + - pmp0cfg + - Physical memory protection 0 config + - 0x0 + - read-write + - Holds the configuration\. + +PMPCFG1:Physical Memory Protection Config 1 Register +-------------------------- +AddressOffset: 'h3a1 +-------------------------- +Description: +-------------------------- +Holds configuration 4-7. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:24 + - pmp7cfg + - Physical memory protection 7 config + - 0x0 + - read-write + - Holds the configuration\. + * - 23:16 + - pmp6cfg + - Physical memory protection 6 config + - 0x0 + - read-write + - Holds the configuration\. + * - 15:8 + - pmp5cfg + - Physical memory protection 5 config + - 0x0 + - read-write + - Holds the configuration\. + * - 7:0 + - pmp4cfg + - Physical memory protection 4 config + - 0x0 + - read-write + - Holds the configuration\. + +PMPCFG2:Physical Memory Protection Config 2 Register +-------------------------- +AddressOffset: 'h3a2 +-------------------------- +Description: +-------------------------- +Holds configuration 8-11. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:24 + - pmp11cfg + - Physical memory protection 11 config + - 0x0 + - read-write + - Holds the configuration\. + * - 23:16 + - pmp10cfg + - Physical memory protection 10 config + - 0x0 + - read-write + - Holds the configuration\. + * - 15:8 + - pmp9cfg + - Physical memory protection 9 config + - 0x0 + - read-write + - Holds the configuration\. + * - 7:0 + - pmp8cfg + - Physical memory protection 8 config + - 0x0 + - read-write + - Holds the configuration\. + +PMPCFG3:Physical Memory Protection Config 3 Register +-------------------------- +AddressOffset: 'h3a3 +-------------------------- +Description: +-------------------------- +Holds configuration 12-15. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:24 + - pmp15cfg + - Physical memory protection 15 config + - 0x0 + - read-write + - Holds the configuration\. + * - 23:16 + - pmp14cfg + - Physical memory protection 14 config + - 0x0 + - read-write + - Holds the configuration\. + * - 15:8 + - pmp13cfg + - Physical memory protection 13 config + - 0x0 + - read-write + - Holds the configuration\. + * - 7:0 + - pmp12cfg + - Physical memory protection 12 config + - 0x0 + - read-write + - Holds the configuration\. + +PMPADDR0:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b0 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR1:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b1 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR2:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b2 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR3:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b3 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR4:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b4 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR5:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b5 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR6:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b6 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR7:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b7 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR8:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b8 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR9:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3b9 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR10:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3ba +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR11:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3bb +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR12:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3bc +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR13:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3bd +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR14:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3be +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +PMPADDR15:Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3bf +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - 0x0 + - read-write,WARL + - Encodes bits 33\-2 of a 34\-bit physical address\. + +ICACHE:Instruction Cache Register +-------------------------- +AddressOffset: 'h7C0 +-------------------------- +Description: +-------------------------- +Custom Register to enable/disable for Icache [bit 0] + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:1 + - reserved_0 + - Reserved + - 0x0 + - read-only + - Reserved + * - 0 + - icache + - Instruction cache + - 0x1 + - read-write + - Custom Register + +MCYCLE:M-mode Cycle counter Register +-------------------------- +AddressOffset: 'hB00 +-------------------------- +Description: +-------------------------- +Counts the number of clock cycles executed by the processor core on which the hart is running. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-write + - Counts the number of clock cycles executed by the processor core\. + +MINSTRET:Machine Instruction Retired counter Register +-------------------------- +AddressOffset: 'hB02 +-------------------------- +Description: +-------------------------- +Counts the number of instructions the hart has retired. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-write + - Counts the number of instructions the hart has retired\. + +MCYCLEH:Upper 32-bits of M-mode Cycle counter Register +-------------------------- +AddressOffset: 'hB80 +-------------------------- +Description: +-------------------------- +Counts the number of clock cycles executed by the processor core on which the hart is running. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-write + - Counts the number of clock cycles executed by the processor core\. + +MINSTRETH:Upper 32-bits of Machine Instruction Retired counter Register +-------------------------- +AddressOffset: 'hB82 +-------------------------- +Description: +-------------------------- +Counts the number of instructions the hart has retired. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-write + - Counts the number of instructions the hart has retired\. + +MHPMCOUNTER3:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb03 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER4:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb04 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER5:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb05 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER6:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb06 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER7:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb07 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER8:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb08 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER9:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb09 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER10:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb0a +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER11:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb0b +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER12:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb0c +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER13:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb0d +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER14:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb0e +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER15:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb0f +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER16:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb10 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER17:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb11 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER18:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb12 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER19:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb13 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER20:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb14 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER21:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb15 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER22:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb16 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER23:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb17 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER24:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb18 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER25:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb19 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER26:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb1a +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER27:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb1b +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER28:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb1c +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER29:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb1d +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER30:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb1e +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTER31:Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb1f +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH3:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb83 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH4:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb84 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH5:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb85 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH6:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb86 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH7:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb87 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH8:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb88 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH9:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb89 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH10:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb8a +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH11:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb8b +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH12:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb8c +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH13:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb8d +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH14:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb8e +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH15:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb8f +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH16:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb90 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH17:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb91 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH18:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb92 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH19:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb93 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH20:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb94 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH21:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb95 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH22:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb96 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH23:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb97 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH24:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb98 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH25:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb99 +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH26:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb9a +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH27:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb9b +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH28:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb9c +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH29:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb9d +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH30:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb9e +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +MHPMCOUNTERH31:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hb9f +-------------------------- +Description: +-------------------------- +Hardware performance event counter only for RV32. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - WARL + - ``Legal Values``: 0\. + +CYCLE:Cycle counter Register +-------------------------- +AddressOffset: 'hC00 +-------------------------- +Description: +-------------------------- +Cycle counter for RDCYCLE instruction. Shadow of mcycle. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-only + - Count + +INSTRET:Instruction Retired counter Register +-------------------------- +AddressOffset: 'hC02 +-------------------------- +Description: +-------------------------- +Instructions-retired counter for RDINSTRET instruction. Shadow of minstret. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-only + - Count + +CYCLEH:Upper 32-bits of Cycle counter Register +-------------------------- +AddressOffset: 'hC80 +-------------------------- +Description: +-------------------------- +Cycle counter for RDCYCLE instruction. Shadow of mcycleh. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-only + - Count + +INSTRETH:Upper 32-bits of Instruction Retired counter Register +-------------------------- +AddressOffset: 'hC82 +-------------------------- +Description: +-------------------------- +Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - 0x0 + - read-only + - Count + +MVENDORID:Machine Vendor ID Register +-------------------------- +AddressOffset: 'hF11 +-------------------------- +Description: +-------------------------- +This register provids the JEDEC manufacturer ID of the provider of the core. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:7 + - bank + - Bank + - 0xC0 + - read-only + - Contain encoding for number of one\-byte continuation codes discarding the parity bit\. + * - 6:0 + - offset + - Offset + - 0x20 + - read-only + - Contain encording for the final byte discarding the parity bit\. + +MARCHID:Machine Architecture ID Register +-------------------------- +AddressOffset: 'hF12 +-------------------------- +Description: +-------------------------- +This register encodes the base microarchitecture of the hart. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - architecture_id + - Architecture id + - 0x3 + - read-only + - Provide Encoding the base microarchitecture of the hart\. + +MIMPID:Machine Implementation ID Register +-------------------------- +AddressOffset: 'hF13 +-------------------------- +Description: +-------------------------- +Provides a unique encoding of the version of the processor implementation. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - implementation + - Implementation + - 0x0 + - read-only + - Provides unique encoding of the version of the processor implementation\. + +MHARTID:Machine Hardware Thread ID Register +-------------------------- +AddressOffset: 'hF14 +-------------------------- +Description: +-------------------------- +This register contains the integer ID of the hardware thread running the code. + +.. list-table:: + :widths: 20 20 15 10 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **Reset** + - **RIGHT** + - **Description** + * - 31:0 + - hart_id + - Hart id + - 0x0 + - read-only + - Contains the integer ID of the hardware thread running the code\. diff --git a/docs/csr-from-ip-xact/embedded/cva6_csr.xml b/docs/csr-from-ip-xact/embedded/cva6_csr.xml new file mode 100644 index 000000000..32bc2c9be --- /dev/null +++ b/docs/csr-from-ip-xact/embedded/cva6_csr.xml @@ -0,0 +1,4884 @@ + + + OpenHW + cva6 + CV32A6_CSR + Apache_2.0_with_SHL_2.1 + + + Other + + + + + + + + + + 32 + + + + + Other + + address_block + 'h0 + 'h4000 + 32 + register + + mstatus + Machine Status + The ``mstatus`` register keeps track of and controls the hart’s current operating state. + 'h300 + 32 + true + read-write + + SD + State Dirty + The SD bit is a read-only bit.``Legal Values``:0. + 31 + + + 0x0 + 0x1 + + + 1 + true + read-only + + + Not_Dirty + None of FS, VS or XS is dirty. + 0 + + + Dirty + Either FS, VS or XS is dirty. + 1 + + + + WARL + + + + reserved_0 + Reserved + Reserved + 23 + + + 0x0 + 0x1 + + + 8 + read-write + + WPRI + + + + TSR + Trap SRET + The TSR bit supports intercepting the supervisor exception return instruction, SRET. + 22 + + + 0x0 + 0x1 + + + 1 + read-write + + + Permitted + Executing SRET in S-mode is permitted. + 0 + + + Not_Permitted + Illegal instruction exception raised by executing SRET in S-mode. + 1 + + + + WARL + + + + TW + Timeout Wait + The TW bit supports intercepting the WFI instruction. + 21 + + + 0x0 + 0x1 + + + 1 + read-write + + + Permitted + WFI may execute in lower privilege modes. + 0 + + + Not_Permitted + Illegal instruction exception raised by executing WFI in lower privilege mode that does not complete in bounded time limit. + 1 + + + + WARL + + + + TVM + Trap Virtual Memory + The TVM bit supports intercepting supervisor virtual-memory management operations. + 20 + + + 0x0 + 0x1 + + + 1 + read-write + + + Permitted + Reading or writing SATP and executing SFENCE.VMA are permitted in S-mode. + 0 + + + Not_Permitted + Illegal instruction exception is raised by reading or writing SATP or executing in S-mode SFENCE.VMA . + 1 + + + + WARL + + + + MXR + Make eXecutable Readable + The MXR bit modifies the privilege with which loads access virtual memory. + 19 + + + 0x0 + 0x1 + + + 1 + read-write + + + Not_Executable + Only loads from pages marked readable will succeed. + 0 + + + Executable + Loads from pages marked either readable or executable will succeed. + 1 + + + + + SUM + Supervisor User Memory + The SUM bit modifies the privilege with which S-mode loads and stores access virtual memory. + 18 + + + 0x0 + 0x1 + + + 1 + read-write + + + Not_Permitted + No access to U-mode pages with S-mode. + 0 + + + Permitted + Access to U-mode pages with S-mode is granted. + 1 + + + + + MPRV + Modify Privilege + The MPRV bit modifies the privilege mode at which loads and stores execute. + 17 + + + 0x0 + 0x1 + + + 1 + read-write + + + Normal + Loads and stores behave as normal. + 0 + + + Protected + Load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP. + 1 + + + + + XS + Extension State + The XS field encodes the status of the additional user-mode extensions and associated state.``Legal Values``:0. + 15 + + + 0x0 + 0x3 + + + 2 + true + read-only + + + Off + All off + 0 + + + Initial + None dirty or clean, some on + 1 + + + Clean + None dirty, some clean + 2 + + + Dirty + Some dirty + 3 + + + + WARL + + + + FS + Floating-point unit State + FS extension is not supported.``Legal Values``:0. + 13 + + + 0x0 + 0x3 + + + 2 + read-only + + + Off + 0 + + + Initial + 1 + + + Clean + 2 + + + Dirty + 3 + + + + WARL + + + + MPP + Machine mode Prior Privilege + Holds the previous privilege mode for machine mode. + 11 + + + 0x0 + 0x3 + + + 2 + read-write + + + U-mode + 0 + + + S-mode + 1 + + + Reserved + 2 + + + M-mode + 3 + + + + + VS + Vector extension State + V extension is not supported.``Legal Values``:0. + 9 + + + 0x0 + 0x3 + + + 2 + read-only + + WARL + + + + SPP + Supervisor mode Prior Privilege + Holds the previous privilege mode for supervisor mode. + 8 + + + 0x0 + 0x1 + + + 1 + read-write + + + U-mode + 0 + + + Otherwise + 1 + + + + + MPIE + Machine mode Prior Interrupt Enable + Indicates whether machine interrupts were enabled prior to trapping into machine mode. + 7 + + + 0x0 + 0x1 + + + 1 + read-write + + + Disabled + Interrupts were not enabled in M-mode. + 0 + + + Enabled + Interrupts were enabled in M-mode. + 1 + + + + + UBE + User mode Bit Endianess + UBE controls whether explicit load and store memory accesses made from U-mode are little-endian or big-endian.``Legal Values``:0. + 6 + + + 0x0 + 0x1 + + + 1 + read-write + + + Little-endian + 0 + + + Big-endian + 1 + + + + WARL + + + + SPIE + Supervisor mode Prior Interrupt Enable + Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. + 5 + + + 0x0 + 0x1 + + + 1 + read-write + + + Disabled + Interrupts were not enabled in S-mode. + 0 + + + Enabled + Interrupts were enabled in S-mode. + 1 + + + + + reserved_1 + Reserved + Reserved + 4 + + + 0x0 + 0x1 + + + 1 + read-write + + WPRI + + + + MIE + Machine mode Interrupt Enable + Global interrupt-enable bit for Machine mode. + 3 + + + 0x0 + 0x1 + + + 1 + read-write + + + Disabled + Interrupts are disabled. + 0 + + + Enabled + Interrupts are enabled. + 1 + + + + + reserved_2 + Reserved + Reserved + 2 + + + 0x0 + 0x1 + + + 1 + read-write + + WPRI + + + + SIE + Supervisor mode Interrupt Enable + Global interrupt-enable bit for Supervisor mode. + 1 + + + 0x0 + 0x1 + + + 1 + read-write + + + Disabled + Interrupts are disabled. + 0 + + + Enabled + Interrupts are enabled. + 1 + + + + + reserved_3 + Reserved + Reserved + 0 + + + 0x0 + 0x1 + + + 1 + read-write + + WPRI + + + + M + + + + misa + Machine ISA + The misa CSR is reporting the ISA supported by the hart. + 'h301 + 32 + read-write + + MXL + Machine XLEN + The MXL field encodes the native base integer ISA width.``Legal Values``:1. + 30 + + + 0x0 + 0x3 + + + 2 + read-write + + + XLEN_32 + 1 + + + XLEN_64 + 2 + + + XLEN_128 + 3 + + + + WARL + + + + Reserved_26 + Reserved + Reserved.``Legal Values:``0. + 26 + + + 0x0 + 0x1 + + + 4 + read-write + + WARL + + + + Extensions + Extensions + The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet.``Legal Values``:0x141104. + 0 + + + 0x141104 + 0x3ffffff + + + 26 + read-write + + + A + Atomic extension. + 1 + + + B + *Tentatively reserved for Bit-Manipulation extension.* + 2 + + + C + Compressed extension. + 4 + + + D + Double-precision floating-point extension. + 8 + + + E + RV32E base ISA. + 16 + + + F + Single-precision floating-point extension. + 32 + + + G + *Reserved.* + 64 + + + H + Hypervisor extension. + 128 + + + I + RV32I/64I/128I base ISA. + 256 + + + J + *Tentatively reserved for Dynamically Translated Languages extension.* + 512 + + + K + *Reserved.* + 1024 + + + L + *Reserved.* + 2048 + + + M + Integer Multiply/Divide extension. + 4096 + + + N + *Tentatively reserved for User-Level Interrupts extension.* + 8192 + + + O + *Reserved.* + 16384 + + + P + *Tentatively reserved for Packed-SIMD extension.* + 32768 + + + Q + Quad-precision floating-point extension. + 65536 + + + R + *Reserved.* + 131072 + + + S + Supervisor mode implemented. + 262144 + + + T + *Reserved.* + 524288 + + + U + User mode implemented. + 1048576 + + + V + *Tentatively reserved for Vector extension.* + 2097152 + + + W + *Reserved.* + 4194304 + + + X + Non-standard extensions present. + 8388608 + + + Y + *Reserved.* + 16777216 + + + Z + *Reserved.* + 33554432 + + + + WARL + + + + M + + + + mie + Machine Interrupt Enable + This register contains machine interrupt enable bits. + 'h304 + 32 + read-write + + Reserved_12 + Reserved + Reserved.``Legal Values:``0. + 12 + + + 0x0 + 0x1 + + + 4 + read-write + + WARL + + + + MEIE + M-mode External Interrupt Enable + Enables machine mode external interrupts. + 11 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + Reserved_10 + Reserved + Reserved.``Legal Values:``0. + 10 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + SEIE + S-mode External Interrupt Enable + Enables supervisor mode external interrupts. + 9 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + UEIE + enables U-mode external interrupts.``Legal Values:``0. + 8 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + MTIE + M-mode Timer Interrupt Enable + Enables machine mode timer interrupts. + 7 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + Reserved_6 + Reserved + Reserved.``Legal Values:``0. + 6 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + STIE + S-mode Timer Interrupt Enable + Enables supervisor mode timer interrupts. + 5 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + UTIE + timer interrupt-enable bit for U-mode.``Legal Values:``0. + 4 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + MSIE + M-mode Software Interrupt Enable + Enables machine mode software interrupts. + 3 + + + 0x0 + 0x1 + + + 1 + read-write + + + Reserved_2 + Reserved + Reserved.``Legal Values:``0. + 2 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + SSIE + S-mode Software Interrupt Enable + Enables supervisor mode software interrupts. + 1 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + USIE + enable U-mode software interrrupts.``Legal Values:``0. + 0 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + M + + + + mtvec + Machine Trap Vector + This register holds trap vector configuration, consisting of a vector base address and a vector mode. + 'h305 + 32 + read-write + + BASE + The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned. + 2 + + + 0x0 + 0x3fffffff + + + 30 + read-write + + WARL + + + + MODE + Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1. + 0 + + + 0x0 + 0x3 + + + 2 + read-write + + + Direct + All exceptions set ``pc`` to BASE. + 0 + + + Vectored + Asynchronous interrupts set ``pc`` to BASE+4×cause. + 1 + + + Reserved_2 + *Reserved.* + 2 + + + Reserved_3 + *Reserved.* + 3 + + + + WARL + + + + M + + + + mstatush + Upper 32-bits of Machine Status + The ``mstatush`` is the upper 32-bits of Machine status only for RV32. + 'h310 + 32 + true + read-write + + reserved_0 + Reserved + Reserved + 0 + + + 0x0 + 0x1 + + + 4 + read-write + + WPRI + + + + SBE + Supervisor mode Bit Endianess + SBE controls whether explicit load and store memory accesses made from S-mode are little-endian or big-endian.``Legal Values``:0. + 4 + + + 0x0 + 0x1 + + + 1 + read-write + + + Little-endian + 0 + + + Big-endian + 1 + + + + WARL + + + + MBE + Machine mode Bit Endianess + MBE controls whether explicit load and store memory accesses made from M-mode are little-endian or big-endian.``Legal Values``:0. + 5 + + + 0x0 + 0x1 + + + 1 + read-write + + + Little-endian + 0 + + + Big-endian + 1 + + + + WARL + + + + reserved_1 + Reserved + Reserved + 6 + + + 0x0 + 0x1 + + + 26 + read-write + + WPRI + + + + M + + + + mhpmevent3 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h323 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent4 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h324 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent5 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h325 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent6 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h326 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent7 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h327 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent8 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h328 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent9 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h329 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent10 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h32a + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent11 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h32b + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent12 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h32c + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent13 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h32d + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent14 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h32e + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent15 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h32f + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent16 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h330 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent17 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h331 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent18 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h332 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent19 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h333 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent20 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h334 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent21 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h335 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent22 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h336 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent23 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h337 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent24 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h338 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent25 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h339 + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent26 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h33a + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent27 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h33b + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent28 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h33c + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent29 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h33d + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent30 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h33e + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmevent31 + Machine Hardware Performance-Monitoring Event Selector + This register controls which event causes the corresponding counter to increment. + 6 + 'h33f + 32 + read-write + + mhpmevent + Event selector CSRs.``Legal Values``:0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mscratch + Machine Scratch + This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception. + 'h340 + 32 + read-write + + mscratch + Machine Scratch + Holds a value dedicated to Machine mode. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + + M + + + + mepc + Machine Exception Program Counter + This register must be able to hold all valid virtual addresses. + 'h341 + 32 + read-write + + mepc + Machine Exception Program Counter + When a trap is taken into M-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + mcause + Machine Cause + When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. +Machine cause register (``mcause``) values after trap are shown in the following table. ========= ============== ============================== +Interrupt Exception Code Description ========= ============== ============================== + 1 0 *Reserved* + 1 1 Supervisor software interrupt + 1 2-4 *Reserved* + 1 5 Supervisor timer interrupt + 1 6-8 *Reserved* + 1 9 Supervisor external interrupt + 1 10-15 *Reserved* + 1 ≥16 *Designated for platform use* + 0 0 Instruction address misaligned + 0 1 Instruction access fault + 0 2 Illegal instruction + 0 3 Breakpoint + 0 4 Load address misaligned + 0 5 Load access fault + 0 6 Store/AMO address misaligned + 0 7 Store/AMO access fault + 0 8 Environment call from U-mode + 0 9 Environment call from S-mode + 0 10-11 *Reserved* + 0 12 Instruction page fault + 0 13 Load page fault + 0 14 *Reserved* + 0 15 Store/AMO page fault + 0 16-23 *Reserved* + 0 24-31 *Designated for custom use* + 0 32-47 *Reserved* + 0 48-63 *Designated for custom use* + 0 ≥64 *Reserved* ========= ============== ============================== + 'h342 + 32 + read-write + + Interrupt + Interrupt + This bit is set if the trap was caused by an interrupt. + 31 + + + 0x0 + 0x1 + + + 1 + read-write + + + exception_code + Exception Code + This field contains a code identifying the last exception or interrupt. + 0 + + + 0x0 + 0x7fffffff + + + 31 + read-write + + WLRL + + + + M + + + + mtval + Machine Trap Value + When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. + 'h343 + 32 + read-write + + mtval + Machine Trap Value + If ``mtval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address. +If ``mtval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault. +If ``mtval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + mip + Machine Interrupt Pending + This register contains machine interrupt pending bits. + 'h344 + 32 + true + read-write + + Reserved_12 + Reserved + Reserved.``Legal Values:``0. + 12 + + + 0x0 + 0x1 + + + 4 + read-write + + WARL + + + + MEIP + M-mode External Interrupt Pending + The interrupt-pending bit for machine-level external interrupts. + 11 + + + 0x0 + 0x1 + + + 1 + true + read-only + + + Reserved_10 + Reserved + Reserved.``Legal Values:``0. + 10 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + SEIP + S-mode External Interrupt Pending + The interrupt-pending bit for supervisor-level external interrupts. + 9 + + + 0x0 + 0x1 + + + 1 + read-write + + + UEIP + enables external interrupts.``Legal Values:``0. + 8 + + + 0x0 + 0x1 + + + 1 + read-write + + + MTIP + M-mode Timer Interrupt Pending + The interrupt-pending bit for machine-level timer interrupts. + 7 + + + 0x0 + 0x1 + + + 1 + true + read-only + + + Reserved_6 + Reserved + Reserved.``Legal Values:``0. + 6 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + STIP + S-mode Timer Interrupt Pending + The interrupt-pending bit for supervisor-level timer interrupts. + 5 + + + 0x0 + 0x1 + + + 1 + read-write + + + UTIP + Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0. + 4 + + + 0x0 + 0x1 + + + 1 + read-write + + + MSIP + M-mode Software Interrupt Pending + The interrupt-pending bit for machine-level software interrupts. + 3 + + + 0x0 + 0x1 + + + 1 + true + read-only + + + Reserved_2 + Reserved + Reserved.``Legal Values:``0. + 2 + + + 0x0 + 0x1 + + + 1 + read-write + + WARL + + + + SSIP + S-mode Software Interrupt Pending + The interrupt-pending bit for supervisor-level software interrupts. + 1 + + + 0x0 + 0x1 + + + 1 + read-write + + + USIP + A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0. + 0 + + + 0x0 + 0x1 + + + 1 + read-write + + + M + + + + pmpcfg0 + Physical Memory Protection Config 0 + Holds configuration 0-3. + 'h3a0 + 32 + read-write + + pmp3cfg + Physical Memory Protection 3 Config + Holds the configuration. + 24 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp2cfg + Physical Memory Protection 2 Config + Holds the configuration. + 16 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp1cfg + Physical Memory Protection 1 Config + Holds the configuration. + 8 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp0cfg + Physical Memory Protection 0 Config + Holds the configuration. + 0 + + + 0x0 + 0xff + + + 8 + read-write + + + M + + + + pmpcfg1 + Physical Memory Protection Config 1 + Holds configuration 4-7. + 'h3a1 + 32 + read-write + + pmp7cfg + Physical Memory Protection 7 Config + Holds the configuration. + 24 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp6cfg + Physical Memory Protection 6 Config + Holds the configuration. + 16 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp5cfg + Physical Memory Protection 5 Config + Holds the configuration. + 8 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp4cfg + Physical Memory Protection 4 Config + Holds the configuration. + 0 + + + 0x0 + 0xff + + + 8 + read-write + + + M + + + + pmpcfg2 + Physical Memory Protection Config 2 + Holds configuration 8-11. + 'h3a2 + 32 + read-write + + pmp11cfg + Physical Memory Protection 11 Config + Holds the configuration. + 24 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp10cfg + Physical Memory Protection 10 Config + Holds the configuration. + 16 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp9cfg + Physical Memory Protection 9 Config + Holds the configuration. + 8 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp8cfg + Physical Memory Protection 8 Config + Holds the configuration. + 0 + + + 0x0 + 0xff + + + 8 + read-write + + + M + + + + pmpcfg3 + Physical Memory Protection Config 3 + Holds configuration 12-15. + 'h3a3 + 32 + read-write + + pmp15cfg + Physical Memory Protection 15 Config + Holds the configuration. + 24 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp14cfg + Physical Memory Protection 14 Config + Holds the configuration. + 16 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp13cfg + Physical Memory Protection 13 Config + Holds the configuration. + 8 + + + 0x0 + 0xff + + + 8 + read-write + + + pmp12cfg + Physical Memory Protection 12 Config + Holds the configuration. + 0 + + + 0x0 + 0xff + + + 8 + read-write + + + M + + + + pmpaddr0 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b0 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr1 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b1 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr2 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b2 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr3 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b3 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr4 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b4 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr5 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b5 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr6 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b6 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr7 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b7 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr8 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b8 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr9 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3b9 + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr10 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3ba + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr11 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3bb + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr12 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3bc + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr13 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3bd + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr14 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3be + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + pmpaddr15 + Physical Memory Protection Address + Address register for Physical Memory Protection. + 16 + 'h3bf + 32 + read-write + + address + Address + Encodes bits 33-2 of a 34-bit physical address. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + WARL + + + + M + + + + icache + Instruction Cache + Custom Register to enable/disable for Icache [bit 0] + 'h7C0 + 32 + read-write + + reserved_0 + Reserved + Reserved + 1 + + + 0x0 + 0x1 + + + 31 + read-only + + + icache + Instruction Cache + Custom Register + 0 + + + 0x1 + 0x1 + + + 1 + read-write + + + M + + + + mcycle + M-mode Cycle counter + Counts the number of clock cycles executed by the processor core on which the hart is running. + 'hB00 + 32 + read-write + + count + Count + Counts the number of clock cycles executed by the processor core. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + + M + + + + minstret + Machine Instruction Retired counter + Counts the number of instructions the hart has retired. + 'hB02 + 32 + read-write + + count + Count + Counts the number of instructions the hart has retired. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + + M + + + + mcycleh + Upper 32-bits of M-mode Cycle counter + Counts the number of clock cycles executed by the processor core on which the hart is running. + 'hB80 + 32 + read-write + + count + Count + Counts the number of clock cycles executed by the processor core. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + + M + + + + minstreth + Upper 32-bits of Machine Instruction Retired counter + Counts the number of instructions the hart has retired. + 'hB82 + 32 + read-write + + count + Count + Counts the number of instructions the hart has retired. + 0 + + + 0x0 + 0xffffffff + + + 32 + read-write + + + M + + + + mhpmcounter3 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb03 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter4 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb04 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter5 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb05 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter6 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb06 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter7 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb07 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter8 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb08 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter9 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb09 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter10 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb0a + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter11 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb0b + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter12 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb0c + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter13 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb0d + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter14 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb0e + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter15 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb0f + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter16 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb10 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter17 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb11 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter18 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb12 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter19 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb13 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter20 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb14 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter21 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb15 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter22 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb16 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter23 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb17 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter24 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb18 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter25 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb19 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter26 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb1a + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter27 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb1b + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter28 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb1c + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter29 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb1d + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter30 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb1e + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounter31 + Machine Hardware Performance Monitoring Counter + Hardware performance event counter. + 6 + 'hb1f + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh3 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb83 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh4 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb84 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh5 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb85 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh6 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb86 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh7 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb87 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh8 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb88 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh9 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb89 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh10 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb8a + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh11 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb8b + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh12 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb8c + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh13 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb8d + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh14 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb8e + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh15 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb8f + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh16 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb90 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh17 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb91 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh18 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb92 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh19 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb93 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh20 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb94 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh21 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb95 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh22 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb96 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh23 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb97 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh24 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb98 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh25 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb99 + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh26 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb9a + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh27 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb9b + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh28 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb9c + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh29 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb9d + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh30 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb9e + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + mhpmcounterh31 + Upper 32 bits of Machine Hardware Performance Monitoring Counter + Hardware performance event counter only for RV32. + 6 + 'hb9f + 32 + read-write + + count + Count + ``Legal Values``: 0. + 0 + + + 0x0 + 0xffffffff + + + 32 + WARL + + + M + + + + cycle + Cycle counter + Cycle counter for RDCYCLE instruction. Shadow of mcycle. + 'hC00 + 32 + true + read-only + + count + Count + Count + 0 + + + 0x0 + 0xffffffff + + + 32 + true + read-only + + + U + + + + instret + Instruction Retired counter + Instructions-retired counter for RDINSTRET instruction. Shadow of minstret. + 'hC02 + 32 + true + read-only + + count + Count + Count + 0 + + + 0x0 + 0xffffffff + + + 32 + true + read-only + + + U + + + + cycleh + Upper 32-bits of Cycle counter + Cycle counter for RDCYCLE instruction. Shadow of mcycleh. + 'hC80 + 32 + true + read-only + + count + Count + Count + 0 + + + 0x0 + 0xffffffff + + + 32 + true + read-only + + + U + + + + instreth + Upper 32-bits of Instruction Retired counter + Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth. + 'hC82 + 32 + true + read-only + + count + Count + Count + 0 + + + 0x0 + 0xffffffff + + + 32 + true + read-only + + + U + + + + mvendorid + Machine Vendor ID + This register provids the JEDEC manufacturer ID of the provider of the core. + 'hF11 + 32 + true + read-only + + bank + Bank + Contain encoding for number of one-byte continuation codes discarding the parity bit. + 7 + + + 0xC0 + 0x1ffffff + + + 25 + true + read-only + + + offset + Offset + Contain encording for the final byte discarding the parity bit. + 0 + + + 0x20 + 0x7f + + + 7 + true + read-only + + + M + + + + marchid + Machine Architecture ID + This register encodes the base microarchitecture of the hart. + 'hF12 + 32 + true + read-only + + architecture_id + Architecture ID + Provide Encoding the base microarchitecture of the hart. + 0 + + + 0x3 + 0xffffffff + + + 32 + true + read-only + + + M + + + + mimpid + Machine Implementation ID + Provides a unique encoding of the version of the processor implementation. + 'hF13 + 32 + true + read-only + + implementation + Implementation + Provides unique encoding of the version of the processor implementation. + 0 + + + 0x0 + 0xffffffff + + + 32 + true + read-only + + + M + + + + mhartid + Machine Hardware Thread ID + This register contains the integer ID of the hardware thread running the code. + 'hF14 + 32 + true + read-only + + hart_id + Hart ID + Contains the integer ID of the hardware thread running the code. + 0 + + + 0x0 + 0xffffffff + + + 32 + true + read-only + + + M + + + + 32 + + + diff --git a/docs/csr-from-ip-xact/embedded/cva6_csr.yaml b/docs/csr-from-ip-xact/embedded/cva6_csr.yaml new file mode 100644 index 000000000..b9284f1e5 --- /dev/null +++ b/docs/csr-from-ip-xact/embedded/cva6_csr.yaml @@ -0,0 +1,3688 @@ +# +# Copyright (c) 2023 Thales Silicon Security +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# Author: Mohamed Aziz FRIKHA +# + +component: + '@xmlns:ipxact': http://www.accellera.org/XMLSchema/IPXACT/1685-2014 + vendor: OpenHW + library: cva6 + name: CV32A6_CSR + version: Apache_2.0_with_SHL_2.1 + busInterfaces: + busInterface: + name: Other + busType: + '@library': cv32a6 + '@name': cva6 + '@vendor': OpenHW + '@version': '1.0' + abstractionTypes: + abstractionType: + abstractionRef: + '@library': cv32a6 + '@name': cva6 + '@vendor': OpenHW + '@version': '1.0' + slave: + memoryMapRef: + '@memoryMapRef': Other + bitsInLau: '32' + memoryMaps: + memoryMap: + name: Other + addressBlock: + name: address_block + baseAddress: "'h0" + range: "'h4000" + width: '32' + usage: register + register: + - name: mstatus + displayName: Machine Status + description: The ``mstatus`` register keeps track of and controls the hart’s current operating state. + addressOffset: "'h300" + size: '32' + volatile: 'true' + access: read-write + field: + - name: SD + displayName: State Dirty + description: The SD bit is a read-only bit.``Legal Values``:0. + bitOffset: '31' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + volatile: 'true' + access: read-only + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Not_Dirty + description: None of FS, VS or XS is dirty. + value: '0' + - '@usage': read + name: Dirty + description: Either FS, VS or XS is dirty. + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: reserved_0 + displayName: Reserved + description: Reserved + bitOffset: '23' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '8' + access: read-write + vendorExtensions: + RISCV_behavior: WPRI + - name: TSR + displayName: Trap SRET + description: The TSR bit supports intercepting the supervisor exception return instruction, SRET. + bitOffset: '22' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Permitted + description: Executing SRET in S-mode is permitted. + value: '0' + - '@usage': read + name: Not_Permitted + description: Illegal instruction exception raised by executing SRET in S-mode. + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: TW + displayName: Timeout Wait + description: The TW bit supports intercepting the WFI instruction. + bitOffset: '21' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Permitted + description: WFI may execute in lower privilege modes. + value: '0' + - '@usage': read + name: Not_Permitted + description: Illegal instruction exception raised by executing WFI in lower privilege mode that does not complete in bounded time limit. + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: TVM + displayName: Trap Virtual Memory + description: The TVM bit supports intercepting supervisor virtual-memory management operations. + bitOffset: '20' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Permitted + description: Reading or writing SATP and executing SFENCE.VMA are permitted in S-mode. + value: '0' + - '@usage': read + name: Not_Permitted + description: Illegal instruction exception is raised by reading or writing SATP or executing in S-mode SFENCE.VMA . + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: MXR + displayName: Make eXecutable Readable + description: The MXR bit modifies the privilege with which loads access virtual memory. + bitOffset: '19' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Not_Executable + description: Only loads from pages marked readable will succeed. + value: '0' + - '@usage': read + name: Executable + description: Loads from pages marked either readable or executable will succeed. + value: '1' + - name: SUM + displayName: Supervisor User Memory + description: The SUM bit modifies the privilege with which S-mode loads and stores access virtual memory. + bitOffset: '18' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Not_Permitted + description: No access to U-mode pages with S-mode. + value: '0' + - '@usage': read + name: Permitted + description: Access to U-mode pages with S-mode is granted. + value: '1' + - name: MPRV + displayName: Modify Privilege + description: The MPRV bit modifies the privilege mode at which loads and stores execute. + bitOffset: '17' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Normal + description: Loads and stores behave as normal. + value: '0' + - '@usage': read + name: Protected + description: Load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP. + value: '1' + - name: XS + displayName: Extension State + description: The XS field encodes the status of the additional user-mode extensions and associated state.``Legal Values``:0. + bitOffset: '15' + resets: + reset: + value: '0x0' + mask: '0x3' + bitWidth: '2' + volatile: 'true' + access: read-only + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Off + description: All off + value: '0' + - '@usage': read + name: Initial + description: None dirty or clean, some on + value: '1' + - '@usage': read + name: Clean + description: None dirty, some clean + value: '2' + - '@usage': read + name: Dirty + description: Some dirty + value: '3' + vendorExtensions: + RISCV_behavior: WARL + - name: FS + displayName: Floating-point unit State + description: FS extension is not supported.``Legal Values``:0. + bitOffset: '13' + resets: + reset: + value: '0x0' + mask: '0x3' + bitWidth: '2' + access: read-only + enumeratedValues: + enumeratedValue: + - '@usage': read-write + name: Off + value: '0' + - '@usage': read-write + name: Initial + value: '1' + - '@usage': read-write + name: Clean + value: '2' + - '@usage': read-write + name: Dirty + value: '3' + vendorExtensions: + RISCV_behavior: WARL + - name: MPP + displayName: Machine mode Prior Privilege + description: Holds the previous privilege mode for machine mode. + bitOffset: '11' + resets: + reset: + value: '0x0' + mask: '0x3' + bitWidth: '2' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read-write + name: U-mode + value: '0' + - '@usage': read-write + name: S-mode + value: '1' + - '@usage': read-write + name: Reserved + value: '2' + - '@usage': read-write + name: M-mode + value: '3' + - name: VS + displayName: Vector extension State + description: V extension is not supported.``Legal Values``:0. + bitOffset: '9' + resets: + reset: + value: '0x0' + mask: '0x3' + bitWidth: '2' + access: read-only + vendorExtensions: + RISCV_behavior: WARL + - name: SPP + displayName: Supervisor mode Prior Privilege + description: Holds the previous privilege mode for supervisor mode. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read-write + name: U-mode + value: '0' + - '@usage': read-write + name: Otherwise + value: '1' + - name: MPIE + displayName: Machine mode Prior Interrupt Enable + description: Indicates whether machine interrupts were enabled prior to trapping into machine mode. + bitOffset: '7' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Disabled + description: Interrupts were not enabled in M-mode. + value: '0' + - '@usage': read + name: Enabled + description: Interrupts were enabled in M-mode. + value: '1' + - name: UBE + displayName: User mode Bit Endianess + description: UBE controls whether explicit load and store memory accesses made from U-mode are little-endian or big-endian.``Legal Values``:0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Little-endian + value: '0' + - '@usage': read + name: Big-endian + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: SPIE + displayName: Supervisor mode Prior Interrupt Enable + description: Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. + bitOffset: '5' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Disabled + description: Interrupts were not enabled in S-mode. + value: '0' + - '@usage': read + name: Enabled + description: Interrupts were enabled in S-mode. + value: '1' + - name: reserved_1 + displayName: Reserved + description: Reserved + bitOffset: '4' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WPRI + - name: MIE + displayName: Machine mode Interrupt Enable + description: Global interrupt-enable bit for Machine mode. + bitOffset: '3' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Disabled + description: Interrupts are disabled. + value: '0' + - '@usage': read + name: Enabled + description: Interrupts are enabled. + value: '1' + - name: reserved_2 + displayName: Reserved + description: Reserved + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WPRI + - name: SIE + displayName: Supervisor mode Interrupt Enable + description: Global interrupt-enable bit for Supervisor mode. + bitOffset: '1' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Disabled + description: Interrupts are disabled. + value: '0' + - '@usage': read + name: Enabled + description: Interrupts are enabled. + value: '1' + - name: reserved_3 + displayName: Reserved + description: Reserved + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WPRI + vendorExtensions: + privilege_mode: M + - name: misa + displayName: Machine ISA + description: The misa CSR is reporting the ISA supported by the hart. + addressOffset: "'h301" + size: '32' + access: read-write + field: + - name: MXL + displayName: Machine XLEN + description: The MXL field encodes the native base integer ISA width.``Legal Values``:1. + bitOffset: '30' + resets: + reset: + value: '0x0' + mask: '0x3' + bitWidth: '2' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read-write + name: XLEN_32 + value: '1' + - '@usage': read-write + name: XLEN_64 + value: '2' + - '@usage': read-write + name: XLEN_128 + value: '3' + vendorExtensions: + RISCV_behavior: WARL + - name: Reserved_26 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '26' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '4' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: Extensions + displayName: Extensions + description: The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet.``Legal Values``:0x141104. + bitOffset: '0' + resets: + reset: + value: '0x141104' + mask: '0x3ffffff' + bitWidth: '26' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read-write + name: A + description: Atomic extension. + value: '1' + - '@usage': read-write + name: B + description: '*Tentatively reserved for Bit-Manipulation extension.*' + value: '2' + - '@usage': read-write + name: C + description: Compressed extension. + value: '4' + - '@usage': read-write + name: D + description: Double-precision floating-point extension. + value: '8' + - '@usage': read-write + name: E + description: RV32E base ISA. + value: '16' + - '@usage': read-write + name: F + description: Single-precision floating-point extension. + value: '32' + - '@usage': read-write + name: G + description: '*Reserved.*' + value: '64' + - '@usage': read-write + name: H + description: Hypervisor extension. + value: '128' + - '@usage': read-write + name: I + description: RV32I/64I/128I base ISA. + value: '256' + - '@usage': read-write + name: J + description: '*Tentatively reserved for Dynamically Translated Languages extension.*' + value: '512' + - '@usage': read-write + name: K + description: '*Reserved.*' + value: '1024' + - '@usage': read-write + name: L + description: '*Reserved.*' + value: '2048' + - '@usage': read-write + name: M + description: Integer Multiply/Divide extension. + value: '4096' + - '@usage': read-write + name: N + description: '*Tentatively reserved for User-Level Interrupts extension.*' + value: '8192' + - '@usage': read-write + name: O + description: '*Reserved.*' + value: '16384' + - '@usage': read-write + name: P + description: '*Tentatively reserved for Packed-SIMD extension.*' + value: '32768' + - '@usage': read-write + name: Q + description: Quad-precision floating-point extension. + value: '65536' + - '@usage': read-write + name: R + description: '*Reserved.*' + value: '131072' + - '@usage': read-write + name: S + description: Supervisor mode implemented. + value: '262144' + - '@usage': read-write + name: T + description: '*Reserved.*' + value: '524288' + - '@usage': read-write + name: U + description: User mode implemented. + value: '1048576' + - '@usage': read-write + name: V + description: '*Tentatively reserved for Vector extension.*' + value: '2097152' + - '@usage': read-write + name: W + description: '*Reserved.*' + value: '4194304' + - '@usage': read-write + name: X + description: Non-standard extensions present. + value: '8388608' + - '@usage': read-write + name: Y + description: '*Reserved.*' + value: '16777216' + - '@usage': read-write + name: Z + description: '*Reserved.*' + value: '33554432' + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: mie + displayName: Machine Interrupt Enable + description: This register contains machine interrupt enable bits. + addressOffset: "'h304" + size: '32' + access: read-write + field: + - name: Reserved_12 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '12' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '4' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: MEIE + displayName: M-mode External Interrupt Enable + description: Enables machine mode external interrupts. + bitOffset: '11' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: Reserved_10 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '10' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: SEIE + displayName: S-mode External Interrupt Enable + description: Enables supervisor mode external interrupts. + bitOffset: '9' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: UEIE + description: enables U-mode external interrupts.``Legal Values:``0. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: MTIE + displayName: M-mode Timer Interrupt Enable + description: Enables machine mode timer interrupts. + bitOffset: '7' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: Reserved_6 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: STIE + displayName: S-mode Timer Interrupt Enable + description: Enables supervisor mode timer interrupts. + bitOffset: '5' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: UTIE + description: timer interrupt-enable bit for U-mode.``Legal Values:``0. + bitOffset: '4' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: MSIE + displayName: M-mode Software Interrupt Enable + description: Enables machine mode software interrupts. + bitOffset: '3' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: Reserved_2 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: SSIE + displayName: S-mode Software Interrupt Enable + description: Enables supervisor mode software interrupts. + bitOffset: '1' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: USIE + description: enable U-mode software interrrupts.``Legal Values:``0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: mtvec + displayName: Machine Trap Vector + description: This register holds trap vector configuration, consisting of a vector base address and a vector mode. + addressOffset: "'h305" + size: '32' + access: read-write + field: + - name: BASE + description: 'The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.' + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x3fffffff' + bitWidth: '30' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: MODE + description: Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0x3' + bitWidth: '2' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read-write + name: Direct + description: All exceptions set ``pc`` to BASE. + value: '0' + - '@usage': read-write + name: Vectored + description: Asynchronous interrupts set ``pc`` to BASE+4×cause. + value: '1' + - '@usage': read-write + name: Reserved_2 + description: '*Reserved.*' + value: '2' + - '@usage': read-write + name: Reserved_3 + description: '*Reserved.*' + value: '3' + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: mstatush + displayName: Upper 32-bits of Machine Status + description: The ``mstatush`` is the upper 32-bits of Machine status only for RV32. + addressOffset: "'h310" + size: '32' + volatile: 'true' + access: read-write + field: + - name: reserved_0 + displayName: Reserved + description: Reserved + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '4' + access: read-write + vendorExtensions: + RISCV_behavior: WPRI + - name: SBE + displayName: Supervisor mode Bit Endianess + description: SBE controls whether explicit load and store memory accesses made from S-mode are little-endian or big-endian.``Legal Values``:0. + bitOffset: '4' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Little-endian + value: '0' + - '@usage': read + name: Big-endian + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: MBE + displayName: Machine mode Bit Endianess + description: MBE controls whether explicit load and store memory accesses made from M-mode are little-endian or big-endian.``Legal Values``:0. + bitOffset: '5' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + enumeratedValues: + enumeratedValue: + - '@usage': read + name: Little-endian + value: '0' + - '@usage': read + name: Big-endian + value: '1' + vendorExtensions: + RISCV_behavior: WARL + - name: reserved_1 + displayName: Reserved + description: Reserved + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '26' + access: read-write + vendorExtensions: + RISCV_behavior: WPRI + vendorExtensions: + privilege_mode: M + - name: mhpmevent3 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h323" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent4 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h324" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent5 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h325" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent6 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h326" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent7 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h327" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent8 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h328" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent9 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h329" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent10 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h32a" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent11 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h32b" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent12 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h32c" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent13 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h32d" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent14 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h32e" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent15 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h32f" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent16 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h330" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent17 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h331" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent18 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h332" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent19 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h333" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent20 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h334" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent21 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h335" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent22 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h336" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent23 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h337" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent24 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h338" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent25 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h339" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent26 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h33a" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent27 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h33b" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent28 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h33c" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent29 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h33d" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent30 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h33e" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmevent31 + displayName: Machine Hardware Performance-Monitoring Event Selector + description: This register controls which event causes the corresponding counter to increment. + dim: '6' + addressOffset: "'h33f" + size: '32' + access: read-write + field: + name: mhpmevent + description: Event selector CSRs.``Legal Values``:0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mscratch + displayName: Machine Scratch + description: This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception. + addressOffset: "'h340" + size: '32' + access: read-write + field: + name: mscratch + displayName: Machine Scratch + description: Holds a value dedicated to Machine mode. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + privilege_mode: M + - name: mepc + displayName: Machine Exception Program Counter + description: This register must be able to hold all valid virtual addresses. + addressOffset: "'h341" + size: '32' + access: read-write + field: + name: mepc + displayName: Machine Exception Program Counter + description: When a trap is taken into M-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: mcause + displayName: Machine Cause + description: "When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap.\nMachine cause register (``mcause``) values after trap are shown in the following table. ========= ============== ==============================\nInterrupt Exception Code Description ========= ============== ==============================\n 1 0 *Reserved*\n 1 1 Supervisor software interrupt\n 1 2-4 *Reserved*\n 1 5 Supervisor timer interrupt\n 1 6-8 *Reserved*\n 1 9 Supervisor external interrupt\n 1 10-15 *Reserved*\n 1 ≥16 *Designated for platform use*\n 0 0 Instruction address misaligned\n 0 1 Instruction access fault\n 0 2 Illegal instruction\n 0 3 Breakpoint\n 0 4 Load address misaligned\n 0 5 Load access fault\n 0 6 Store/AMO address misaligned\n 0 7 Store/AMO access fault\n 0 8 Environment call from U-mode\n 0 9 Environment call from S-mode\n 0 10-11 *Reserved*\n 0 12 Instruction page fault\n 0 13 Load page fault\n 0 14 *Reserved*\n 0 15 Store/AMO page fault\n 0 16-23 *Reserved*\n 0 24-31 *Designated for custom use*\n 0 32-47 *Reserved*\n 0 48-63 *Designated for custom use*\n 0 ≥64 *Reserved* ========= ============== ==============================" + addressOffset: "'h342" + size: '32' + access: read-write + field: + - name: Interrupt + displayName: Interrupt + description: This bit is set if the trap was caused by an interrupt. + bitOffset: '31' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: exception_code + displayName: Exception Code + description: This field contains a code identifying the last exception or interrupt. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0x7fffffff' + bitWidth: '31' + access: read-write + vendorExtensions: + RISCV_behavior: WLRL + vendorExtensions: + privilege_mode: M + - name: mtval + displayName: Machine Trap Value + description: When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. + addressOffset: "'h343" + size: '32' + access: read-write + field: + name: mtval + displayName: Machine Trap Value + description: "If ``mtval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address.\nIf ``mtval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault.\nIf ``mtval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction." + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: mip + displayName: Machine Interrupt Pending + description: This register contains machine interrupt pending bits. + addressOffset: "'h344" + size: '32' + volatile: 'true' + access: read-write + field: + - name: Reserved_12 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '12' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '4' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: MEIP + displayName: M-mode External Interrupt Pending + description: The interrupt-pending bit for machine-level external interrupts. + bitOffset: '11' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + volatile: 'true' + access: read-only + - name: Reserved_10 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '10' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: SEIP + displayName: S-mode External Interrupt Pending + description: The interrupt-pending bit for supervisor-level external interrupts. + bitOffset: '9' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: UEIP + description: enables external interrupts.``Legal Values:``0. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: MTIP + displayName: M-mode Timer Interrupt Pending + description: The interrupt-pending bit for machine-level timer interrupts. + bitOffset: '7' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + volatile: 'true' + access: read-only + - name: Reserved_6 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '6' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: STIP + displayName: S-mode Timer Interrupt Pending + description: The interrupt-pending bit for supervisor-level timer interrupts. + bitOffset: '5' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: UTIP + description: Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0. + bitOffset: '4' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: MSIP + displayName: M-mode Software Interrupt Pending + description: The interrupt-pending bit for machine-level software interrupts. + bitOffset: '3' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + volatile: 'true' + access: read-only + - name: Reserved_2 + displayName: Reserved + description: Reserved.``Legal Values:``0. + bitOffset: '2' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + - name: SSIP + displayName: S-mode Software Interrupt Pending + description: The interrupt-pending bit for supervisor-level software interrupts. + bitOffset: '1' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + - name: USIP + description: A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + privilege_mode: M + - name: pmpcfg0 + displayName: Physical Memory Protection Config 0 + description: Holds configuration 0-3. + addressOffset: "'h3a0" + size: '32' + access: read-write + field: + - name: pmp3cfg + displayName: Physical Memory Protection 3 Config + description: Holds the configuration. + bitOffset: '24' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp2cfg + displayName: Physical Memory Protection 2 Config + description: Holds the configuration. + bitOffset: '16' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp1cfg + displayName: Physical Memory Protection 1 Config + description: Holds the configuration. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp0cfg + displayName: Physical Memory Protection 0 Config + description: Holds the configuration. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + vendorExtensions: + privilege_mode: M + - name: pmpcfg1 + displayName: Physical Memory Protection Config 1 + description: Holds configuration 4-7. + addressOffset: "'h3a1" + size: '32' + access: read-write + field: + - name: pmp7cfg + displayName: Physical Memory Protection 7 Config + description: Holds the configuration. + bitOffset: '24' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp6cfg + displayName: Physical Memory Protection 6 Config + description: Holds the configuration. + bitOffset: '16' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp5cfg + displayName: Physical Memory Protection 5 Config + description: Holds the configuration. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp4cfg + displayName: Physical Memory Protection 4 Config + description: Holds the configuration. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + vendorExtensions: + privilege_mode: M + - name: pmpcfg2 + displayName: Physical Memory Protection Config 2 + description: Holds configuration 8-11. + addressOffset: "'h3a2" + size: '32' + access: read-write + field: + - name: pmp11cfg + displayName: Physical Memory Protection 11 Config + description: Holds the configuration. + bitOffset: '24' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp10cfg + displayName: Physical Memory Protection 10 Config + description: Holds the configuration. + bitOffset: '16' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp9cfg + displayName: Physical Memory Protection 9 Config + description: Holds the configuration. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp8cfg + displayName: Physical Memory Protection 8 Config + description: Holds the configuration. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + vendorExtensions: + privilege_mode: M + - name: pmpcfg3 + displayName: Physical Memory Protection Config 3 + description: Holds configuration 12-15. + addressOffset: "'h3a3" + size: '32' + access: read-write + field: + - name: pmp15cfg + displayName: Physical Memory Protection 15 Config + description: Holds the configuration. + bitOffset: '24' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp14cfg + displayName: Physical Memory Protection 14 Config + description: Holds the configuration. + bitOffset: '16' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp13cfg + displayName: Physical Memory Protection 13 Config + description: Holds the configuration. + bitOffset: '8' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + - name: pmp12cfg + displayName: Physical Memory Protection 12 Config + description: Holds the configuration. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xff' + bitWidth: '8' + access: read-write + vendorExtensions: + privilege_mode: M + - name: pmpaddr0 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b0" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr1 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b1" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr2 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b2" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr3 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b3" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr4 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b4" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr5 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b5" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr6 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b6" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr7 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b7" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr8 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b8" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr9 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3b9" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr10 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3ba" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr11 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3bb" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr12 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3bc" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr13 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3bd" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr14 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3be" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: pmpaddr15 + displayName: Physical Memory Protection Address + description: Address register for Physical Memory Protection. + dim: '16' + addressOffset: "'h3bf" + size: '32' + access: read-write + field: + name: address + displayName: Address + description: Encodes bits 33-2 of a 34-bit physical address. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + RISCV_behavior: WARL + vendorExtensions: + privilege_mode: M + - name: icache + displayName: Instruction Cache + description: Custom Register to enable/disable for Icache [bit 0] + addressOffset: "'h7C0" + size: '32' + access: read-write + field: + - name: reserved_0 + displayName: Reserved + description: Reserved + bitOffset: '1' + resets: + reset: + value: '0x0' + mask: '0x1' + bitWidth: '31' + access: read-only + - name: icache + displayName: Instruction Cache + description: Custom Register + bitOffset: '0' + resets: + reset: + value: '0x1' + mask: '0x1' + bitWidth: '1' + access: read-write + vendorExtensions: + privilege_mode: M + - name: mcycle + displayName: M-mode Cycle counter + description: Counts the number of clock cycles executed by the processor core on which the hart is running. + addressOffset: "'hB00" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: Counts the number of clock cycles executed by the processor core. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + privilege_mode: M + - name: minstret + displayName: Machine Instruction Retired counter + description: Counts the number of instructions the hart has retired. + addressOffset: "'hB02" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: Counts the number of instructions the hart has retired. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + privilege_mode: M + - name: mcycleh + displayName: Upper 32-bits of M-mode Cycle counter + description: Counts the number of clock cycles executed by the processor core on which the hart is running. + addressOffset: "'hB80" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: Counts the number of clock cycles executed by the processor core. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + privilege_mode: M + - name: minstreth + displayName: Upper 32-bits of Machine Instruction Retired counter + description: Counts the number of instructions the hart has retired. + addressOffset: "'hB82" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: Counts the number of instructions the hart has retired. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: read-write + vendorExtensions: + privilege_mode: M + - name: mhpmcounter3 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb03" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter4 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb04" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter5 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb05" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter6 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb06" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter7 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb07" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter8 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb08" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter9 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb09" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter10 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb0a" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter11 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb0b" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter12 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb0c" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter13 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb0d" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter14 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb0e" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter15 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb0f" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter16 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb10" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter17 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb11" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter18 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb12" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter19 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb13" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter20 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb14" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter21 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb15" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter22 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb16" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter23 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb17" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter24 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb18" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter25 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb19" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter26 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb1a" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter27 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb1b" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter28 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb1c" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter29 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb1d" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter30 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb1e" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounter31 + displayName: Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter. + dim: '6' + addressOffset: "'hb1f" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh3 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb83" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh4 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb84" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh5 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb85" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh6 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb86" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh7 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb87" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh8 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb88" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh9 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb89" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh10 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb8a" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh11 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb8b" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh12 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb8c" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh13 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb8d" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh14 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb8e" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh15 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb8f" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh16 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb90" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh17 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb91" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh18 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb92" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh19 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb93" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh20 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb94" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh21 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb95" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh22 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb96" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh23 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb97" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh24 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb98" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh25 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb99" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh26 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb9a" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh27 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb9b" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh28 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb9c" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh29 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb9d" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh30 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb9e" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: mhpmcounterh31 + displayName: Upper 32 bits of Machine Hardware Performance Monitoring Counter + description: Hardware performance event counter only for RV32. + dim: '6' + addressOffset: "'hb9f" + size: '32' + access: read-write + field: + name: count + displayName: Count + description: '``Legal Values``: 0.' + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + access: WARL + vendorExtensions: + privilege_mode: M + - name: cycle + displayName: Cycle counter + description: Cycle counter for RDCYCLE instruction. Shadow of mcycle. + addressOffset: "'hC00" + size: '32' + volatile: 'true' + access: read-only + field: + name: count + displayName: Count + description: Count + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: U + - name: instret + displayName: Instruction Retired counter + description: Instructions-retired counter for RDINSTRET instruction. Shadow of minstret. + addressOffset: "'hC02" + size: '32' + volatile: 'true' + access: read-only + field: + name: count + displayName: Count + description: Count + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: U + - name: cycleh + displayName: Upper 32-bits of Cycle counter + description: Cycle counter for RDCYCLE instruction. Shadow of mcycleh. + addressOffset: "'hC80" + size: '32' + volatile: 'true' + access: read-only + field: + name: count + displayName: Count + description: Count + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: U + - name: instreth + displayName: Upper 32-bits of Instruction Retired counter + description: Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth. + addressOffset: "'hC82" + size: '32' + volatile: 'true' + access: read-only + field: + name: count + displayName: Count + description: Count + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: U + - name: mvendorid + displayName: Machine Vendor ID + description: This register provids the JEDEC manufacturer ID of the provider of the core. + addressOffset: "'hF11" + size: '32' + volatile: 'true' + access: read-only + field: + - name: bank + displayName: Bank + description: Contain encoding for number of one-byte continuation codes discarding the parity bit. + bitOffset: '7' + resets: + reset: + value: '0xC0' + mask: '0x1ffffff' + bitWidth: '25' + volatile: 'true' + access: read-only + - name: offset + displayName: Offset + description: Contain encording for the final byte discarding the parity bit. + bitOffset: '0' + resets: + reset: + value: '0x20' + mask: '0x7f' + bitWidth: '7' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: M + - name: marchid + displayName: Machine Architecture ID + description: This register encodes the base microarchitecture of the hart. + addressOffset: "'hF12" + size: '32' + volatile: 'true' + access: read-only + field: + name: architecture_id + displayName: Architecture ID + description: Provide Encoding the base microarchitecture of the hart. + bitOffset: '0' + resets: + reset: + value: '0x3' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: M + - name: mimpid + displayName: Machine Implementation ID + description: Provides a unique encoding of the version of the processor implementation. + addressOffset: "'hF13" + size: '32' + volatile: 'true' + access: read-only + field: + name: implementation + displayName: Implementation + description: Provides unique encoding of the version of the processor implementation. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: M + - name: mhartid + displayName: Machine Hardware Thread ID + description: This register contains the integer ID of the hardware thread running the code. + addressOffset: "'hF14" + size: '32' + volatile: 'true' + access: read-only + field: + name: hart_id + displayName: Hart ID + description: Contains the integer ID of the hardware thread running the code. + bitOffset: '0' + resets: + reset: + value: '0x0' + mask: '0xffffffff' + bitWidth: '32' + volatile: 'true' + access: read-only + vendorExtensions: + privilege_mode: M + addressUnitBits: '32' diff --git a/docs/csr-from-ip-xact/embedded/cva6_csr_list.rst b/docs/csr-from-ip-xact/embedded/cva6_csr_list.rst new file mode 100644 index 000000000..69ac07d35 --- /dev/null +++ b/docs/csr-from-ip-xact/embedded/cva6_csr_list.rst @@ -0,0 +1,42 @@ +.. code-block:: none + + Copyright (c) 2023 Thales Silicon Security + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + Author: Jean-Roch COULON + + +Register Summary +---------------- +.. csv-table:: + :widths: auto + :align: left + :header: "Name", "Display Name", "Address Offset" + + "``MSTATUS``", "Machine Status Register", "0x300" + "``MISA``", "Machine ISA Register", "0x301" + "``MIE``", "Machine Interrupt Enable Register", "0x304" + "``MTVEC``", "Machine Trap Vector Register", "0x305" + "``MSTATUSH``", "Upper 32-bits of Machine Status Register", "0x310" + "``MHPMEVENT3-31``", "Machine HW Perf Monitoring Event Selector", "0x323-0x33f" + "``MSCRATCH``", "Machine Scratch", "0x340" + "``MEPC``", "Machine Exception Program Counter", "0x341" + "``MCAUSE``", "Machine Cause", "0x342" + "``MTVAL``", "Machine Trap Value", "0x343" + "``MIP``", "Machine Interrupt Pending", "0x344" + "``PMPCFG0-3``", "Physical Memory Protection Config 0", "0x3a0-0x3a3" + "``PMPADDR0-15``", "Physical Memory Protection Address", "0x3b0-0x3bf" + "``ICACHE``", "Instruction Cache", "0x7C0" + "``MCYCLE``", "M-mode Cycle counter", "0xB00" + "``MINSTRET``", "Machine Instruction Retired counter", "0xB02" + "``MCYCLEH``", "Upper 32-bits of M-mode Cycle counter", "0xB80" + "``MINSTRETH``", "Upper 32-bits of Machine Instruction Retired counter", "0xB82" + "``MHPMCOUNTER3-31``", "Machine HW Performance Monitoring Counter", "0xb03-0xb1f" + "``MHPMCOUNTERH3-31``", "Upper 32 bits of Machine HW Perf Monitoring Counter", "0xb83-0xb9f" + "``CYCLE``", "Cycle counter", "0xC00" + "``INSTRET``", "Instruction Retired counter", "0xC02" + "``CYCLEH``", "Upper 32-bits of Cycle counter", "0xC80" + "``INSTRETH``", "Upper 32-bits of Instruction Retired counter", "0xC82" + "``MVENDORID``", "Machine Vendor ID", "0xF11" + "``MARCHID``", "Machine Architecture ID", "0xF12" + "``MIMPID``", "Machine Implementation ID", "0xF13" + "``MHARTID``", "Machine HW Thread ID", "0xF14"