From 9acc57937b115564799cbd00522cb65f65a7df5f Mon Sep 17 00:00:00 2001 From: Florian Zaruba Date: Fri, 19 Apr 2019 16:05:58 +0200 Subject: [PATCH] perf_counters: Add optional return address encoding Either `x1` or `x5` can be used as a return address. --- src/perf_counters.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/perf_counters.sv b/src/perf_counters.sv index 2b010cbcb..ad8fabdb2 100644 --- a/src/perf_counters.sv +++ b/src/perf_counters.sv @@ -82,11 +82,12 @@ module perf_counters #( // The standard software calling convention uses register x1 to hold the return address on a call // the unconditional jump is decoded as ADD op - if (commit_instr_i[i].fu == CTRL_FLOW && commit_instr_i[i].op == '0 && commit_instr_i[i].rd == 'b1) + if (commit_instr_i[i].fu == CTRL_FLOW && commit_instr_i[i].op == '0 + && (commit_instr_i[i].rd == 'd1 || commit_instr_i[i].rd == 'd1)) perf_counter_d[riscv::CSR_CALL[4:0]] = perf_counter_q[riscv::CSR_CALL[4:0]] + 1'b1; // Return from call - if (commit_instr_i[i].op == JALR && commit_instr_i[i].rs1 == 'b1) + if (commit_instr_i[i].op == JALR && (commit_instr_i[i].rd == 'd1 || commit_instr_i[i].rd == 'd1)) perf_counter_d[riscv::CSR_RET[4:0]] = perf_counter_q[riscv::CSR_RET[4:0]] + 1'b1; end end