diff --git a/Makefile b/Makefile index 46a1a46ee..bb4a9191b 100755 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ ariane_pkg := include/riscv_pkg.sv \ src/debug/dm_pkg.sv \ include/ariane_pkg.sv \ include/std_cache_pkg.sv \ - include/axi_if.sv + include/axi_if.sv # utility modules util := $(wildcard src/util/*.svh) \ @@ -41,7 +41,7 @@ dpi_hdr := $(wildcard tb/dpi/*.h) # this list contains the standalone components src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ $(wildcard src/cache_subsystem/*.sv) \ - $(wildcard bootrom/*.sv) \ + $(wildcard bootrom/*.sv) \ $(wildcard src/axi_slice/*.sv) \ $(wildcard src/clint/*.sv) \ $(wildcard src/axi_node/*.sv) \ diff --git a/src/cache_subsystem/std_icache.sv b/src/cache_subsystem/std_icache.sv index 81ebbf80a..577fb001a 100644 --- a/src/cache_subsystem/std_icache.sv +++ b/src/cache_subsystem/std_icache.sv @@ -368,12 +368,6 @@ module std_icache #( tag = tag_q; state_d = TAG_CMP_SAVED; // do tag comparison on the saved tag end - // we need to wait for some AXI responses to come back - // here for the AW valid - WAIT_KILLED_REFILL: begin - if (axi.aw_valid) - state_d = IDLE; - end // ~> we are coming here after reset or when a flush was requested FLUSH: begin addr = cnt_q; diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv index fdc7e07e9..45120ee4b 100644 --- a/src/csr_regfile.sv +++ b/src/csr_regfile.sv @@ -105,7 +105,9 @@ module csr_regfile #( riscv::status_rv64_t mstatus_q, mstatus_d; riscv::satp_t satp_q, satp_d; riscv::dcsr_t dcsr_q, dcsr_d; - + + logic mtvec_rst_load_q;// used to determine whether we came out of reset + logic [63:0] dpc_q, dpc_d; logic [63:0] dscratch0_q, dscratch0_d; logic [63:0] mtvec_q, mtvec_d; @@ -243,7 +245,19 @@ module csr_regfile #( dpc_d = dpc_q; dscratch0_d = dscratch0_q; mstatus_d = mstatus_q; - mtvec_d = mtvec_q; + + // check whether we come out of reset + // this is a workaround. some tools have issues + // having boot_addr_i in the asynchronous + // reset assignment to mtvec_d, even though + // boot_addr_i will be assigned a constant + // on the top-level. + if (mtvec_rst_load_q) begin + mtvec_d = boot_addr_i + 'h40; + end else begin + mtvec_d = mtvec_q; + end + medeleg_d = medeleg_q; mideleg_d = mideleg_q; mip_d = mip_q; @@ -833,7 +847,8 @@ module csr_regfile #( // machine mode registers mstatus_q <= 64'b0; // set to boot address + direct mode + 4 byte offset which is the initial trap - mtvec_q <= boot_addr_i + 'h40; + mtvec_rst_load_q <= 1'b1; + mtvec_q <= '0; medeleg_q <= 64'b0; mideleg_q <= 64'b0; mip_q <= 64'b0; @@ -867,6 +882,7 @@ module csr_regfile #( dscratch0_q <= dscratch0_d; // machine mode registers mstatus_q <= mstatus_d; + mtvec_rst_load_q <= 1'b0; mtvec_q <= mtvec_d; medeleg_q <= medeleg_d; mideleg_q <= mideleg_d; diff --git a/src/decoder.sv b/src/decoder.sv index 544b98acc..815d10d1b 100644 --- a/src/decoder.sv +++ b/src/decoder.sv @@ -66,7 +66,7 @@ module decoder ( instruction_o.fu = NONE; instruction_o.op = ADD; instruction_o.rs1 = '0; - instruction_o.rs2[4:0] = '0; + instruction_o.rs2 = '0; instruction_o.rd = '0; instruction_o.use_pc = 1'b0; instruction_o.trans_id = '0; diff --git a/src/frontend.sv b/src/frontend.sv index 4884b4fe8..119ff5bb6 100644 --- a/src/frontend.sv +++ b/src/frontend.sv @@ -66,6 +66,7 @@ module frontend ( // instruction fetch is ready logic if_ready; logic [63:0] npc_d, npc_q; // next PC + logic npc_rst_load_q; //indicates whether we come out of reset (then we need to load boot_addr_i) // ----------------------- // Ctrl Flow Speculation // ----------------------- @@ -299,9 +300,21 @@ module frontend ( always_comb begin : npc_select automatic logic [63:0] fetch_address; - fetch_address = npc_q; - // keep stable by default - npc_d = npc_q; + // check whether we come out of reset + // this is a workaround. some tools have issues + // having boot_addr_i in the asynchronous + // reset assignment to npc_q, even though + // boot_addr_i will be assigned a constant + // on the top-level. + if (npc_rst_load_q) begin + npc_d = boot_addr_i; + fetch_address = boot_addr_i; + end else begin + fetch_address = npc_q; + // keep stable by default + npc_d = npc_q; + end + // ------------------------------- // 1. Branch Prediction // ------------------------------- @@ -392,10 +405,10 @@ module frontend ( `endif //pragma translate_on - always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin - npc_q <= boot_addr_i; + npc_q <= '0; + npc_rst_load_q <= 1'b1; icache_data_q <= '0; icache_valid_q <= 1'b0; icache_vaddr_q <= 'b0; @@ -406,6 +419,7 @@ module frontend ( fifo_credits_q <= FETCH_FIFO_DEPTH; s2_in_flight_q <= 1'b0; end else begin + npc_rst_load_q <= 1'b0; npc_q <= npc_d; icache_data_q <= icache_dreq_i.data; icache_valid_q <= icache_dreq_i.valid; @@ -471,7 +485,6 @@ module frontend ( fifo_v2 #( .DEPTH ( 8 ), - .ALM_EMPTY_TH ( 8-4 ), .dtype ( fetch_entry_t )) i_fetch_fifo ( .clk_i ( clk_i ), diff --git a/src/load_unit.sv b/src/load_unit.sv index 915d7f1d6..6d8eb960d 100644 --- a/src/load_unit.sv +++ b/src/load_unit.sv @@ -56,6 +56,7 @@ module load_unit ( assign vaddr_o = lsu_ctrl_i.vaddr; // this is a read-only interface so set the write enable to 0 assign req_port_o.data_we = 1'b0; + assign req_port_o.data_wdata = '0; // compose the queue data, control is handled in the FSM assign in_data = {lsu_ctrl_i.trans_id, lsu_ctrl_i.vaddr[2:0], lsu_ctrl_i.operator}; // output address