diff --git a/CHANGELOG.md b/CHANGELOG.md
index 87eeaeea5..3e4839c4d 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -6,6 +6,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## [Unreleased]
 
+### Added
+
+### Changed
+
+- Fix non-setable MEIE bit in MIE CSR
+
 ### 4.2.0 - 2019-06-04
 
 ### Added
diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv
index 14cd66863..38924eb69 100644
--- a/src/csr_regfile.sv
+++ b/src/csr_regfile.sv
@@ -488,7 +488,7 @@ module csr_regfile #(
                 end
                 // mask the register so that unsupported interrupts can never be set
                 riscv::CSR_MIE: begin
-                    mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP | riscv::MIP_MSIP | riscv::MIP_MTIP;
+                    mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP | riscv::MIP_MSIP | riscv::MIP_MTIP | riscv::MIP_MEIP;
                     mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts
                 end