diff --git a/Makefile b/Makefile index 107b9a478..6a392d3c1 100644 --- a/Makefile +++ b/Makefile @@ -32,7 +32,8 @@ test_case = alu_test # QuestaSim Version questa_version = -10.5c compile_flag = +cover=bcfst+/dut - +# Moore binary +moore = ~fschuiki/bin/moore # Iterate over all include directories and write them with +incdir+ prefixed # +incdir+ works for Verilator and QuestaSim list_incdir = $(foreach dir, ${incdir}, +incdir+$(dir)) @@ -70,6 +71,10 @@ $(tests): # vsim${questa_version} +UVM_TESTNAME=$@_test -coverage -classdebug $@_tb_optimized vsim${questa_version} +UVM_TESTNAME=$@_test +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $@_tb_optimized +build-moore: + # $(moore) compile src/fifo.sv + $(foreach src_file, $(src), $(moore) compile $(src_file);) + # User Verilator to lint the target lint: verilator ${src} --lint-only \ @@ -79,4 +84,4 @@ clean: rm -rf work/ *.ucdb .PHONY: - build lint + build lint build-moore diff --git a/include/ariane_pkg.svh b/include/ariane_pkg.svh index 79cba5ae9..8e9297f06 100644 --- a/include/ariane_pkg.svh +++ b/include/ariane_pkg.svh @@ -16,6 +16,7 @@ package ariane_pkg; localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits // to uniquely identify the entry in the scoreboard localparam NR_WB_PORTS = 3; + localparam ASID_WIDTH = 1; localparam ISA_CODE = (1 << 2) // C - Compressed extension | (1 << 8) // I - RV32I/64I/128I base ISA | (1 << 12) // M - Integer Multiply/Divide extension diff --git a/src/ariane.sv b/src/ariane.sv index c6fe206e8..ac1dafdae 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -126,7 +126,6 @@ module ariane logic [TRANS_ID_BITS-1:0] csr_trans_id_ex_id; logic [63:0] csr_result_ex_id; logic csr_valid_ex_id; - // -------------- // EX <-> COMMIT // -------------- @@ -163,7 +162,19 @@ module ariane logic [0:0] asid_csr_ex; logic flush_tlb_csr_ex; logic [11:0] csr_addr_ex_csr; - + // -------------- + // COMMIT <-> CSR + // -------------- + exception ex_commit_csr; + fu_op csr_op_commit_csr; + logic [63:0] csr_wdata_commit_csr; + logic [63:0] csr_rdata_csr_commit; + logic [63:0] pc_commit_csr; + logic [3:0] irq_enable_csr_commit; + exception csr_exception_csr_commit; + // -------------- + // EX <-> CSR + // -------------- // TODO: Preliminary signal assignments logic flush_tlb; @@ -172,7 +183,13 @@ module ariane assign id_ready_i = 1'b1; assign halt_if = 1'b0; + // -------------- + // NPC Generation + // -------------- + // --------- + // IF + // --------- if_stage if_stage_i ( .flush_i ( flush ), .req_i ( fetch_enable ), @@ -195,7 +212,9 @@ module ariane .boot_addr_i ( boot_addr_i ), // TODO .* ); - + // --------- + // ID + // --------- id_stage #( .NR_ENTRIES ( NR_SB_ENTRIES ), @@ -226,13 +245,13 @@ module ariane .mult_ready_i ( ), .mult_valid_o ( ), - .csr_ready_i ( ), - .csr_valid_o ( ), + .csr_ready_i ( csr_ready_ex_id ), + .csr_valid_o ( csr_valid_id_ex ), - .trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id} ), - .wdata_i ( {alu_result_ex_id, lsu_result_ex_id} ), - .ex_ex_i ( {'b0, lsu_exception_ex_id } ), - .wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id} ), + .trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id , csr_trans_id_ex_id} ), + .wdata_i ( {alu_result_ex_id, lsu_result_ex_id, csr_result_ex_id} ), + .ex_ex_i ( {'b0, lsu_exception_ex_id, 'b0 } ), + .wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, csr_valid_ex_id} ), .waddr_a_i ( waddr_a_commit_id ), .wdata_a_i ( wdata_a_commit_id ), @@ -242,15 +261,9 @@ module ariane .commit_ack_i ( commit_ack_commit_id ), .* ); - - - - - - - - - + // --------- + // EX + // --------- ex_stage ex_stage_i ( .flush_i ( flush ), .operator_i ( operator_id_ex ), @@ -282,7 +295,7 @@ module ariane .csr_addr_o ( csr_addr_ex_csr ), .csr_commit_i ( csr_commit_commit_ex ), // from commit // memory management - .enable_translation_i ( 1'b0 ), // from CSR + .enable_translation_i ( enable_translation_csr_ex ), // from CSR .fetch_req_i ( fetch_req_if_ex ), .fetch_gnt_o ( fetch_gnt_ex_if ), .fetch_valid_o ( fetch_valid_ex_if ), @@ -300,17 +313,57 @@ module ariane .mult_valid_i ( mult_valid_id_ex ), .* ); - + // --------- + // Commit + // --------- commit_stage commit_stage_i ( .priv_lvl_o ( priv_lvl ), - .exception_o ( ), + .exception_o ( ex_commit_csr ), .commit_instr_i ( commit_instr_id_commit ), .commit_ack_o ( commit_ack_commit_id ), .waddr_a_o ( waddr_a_commit_id ), .wdata_a_o ( wdata_a_commit_id ), .we_a_o ( we_a_commit_id ), + .commit_lsu_o ( lsu_commit_commit_ex ), + .commit_csr_o ( csr_commit_commit_ex ), + .pc_o ( pc_commit_csr ), + .csr_op_o ( csr_op_commit_csr ), + .csr_wdata_o ( csr_wdata_commit_csr ), + .csr_rdata_i ( csr_rdata_csr_commit ), + .csr_exception_i ( csr_exception_csr_commit ), + .irq_enable_i ( irq_enable_csr_commit ), .* ); + // --------- + // CSR + // --------- + csr_regfile #( + .ASID_WIDTH ( ASID_WIDTH ) + ) + csr_regfile_i ( + .ex_i ( ex_commit_csr ), + .csr_op_i ( csr_op_commit_csr ), + .csr_addr_i ( csr_addr_ex_csr ), + .csr_wdata_i ( csr_wdata_commit_csr ), + .csr_rdata_o ( csr_rdata_csr_commit ), + .pc_i ( pc_commit_csr ), + .csr_exception_o ( csr_exception_o ), + .irq_enable_o ( irq_enable_o ), + .epc_o ( ), + .trap_vector_base_o ( ), + .priv_lvl_o ( priv_lvl ), + + .enable_translation_o ( enable_translation_csr_ex ), + .flag_pum_o ( flag_pum_csr_ex ), + .flag_mxr_o ( flag_mxr_csr_ex ), + .pd_ppn_o ( pd_ppn_csr_ex ), + .asid_o ( asid_csr_ex ), + .* + ); + // ------------ + // Controller + // ------------ + always_ff @(posedge clk_i or negedge rst_ni) begin if(~rst_ni) begin diff --git a/src/commit_stage.sv b/src/commit_stage.sv index bdbd1d58e..c3b6236c9 100644 --- a/src/commit_stage.sv +++ b/src/commit_stage.sv @@ -32,13 +32,24 @@ module commit_stage ( // to register file output logic[4:0] waddr_a_o, output logic[63:0] wdata_a_o, - output logic we_a_o + output logic we_a_o, + // to/from CSR file + output logic [63:0] pc_o, + input fu_op csr_op_o, + output logic [63:0] csr_wdata_o, + output logic [63:0] csr_rdata_i, + input exception csr_exception_i, + // to ex + output logic commit_lsu_o, + output logic commit_csr_o, + // general control signal + input logic [4:0] irq_enable_i ); assign waddr_a_o = commit_instr_i.rd; assign wdata_a_o = commit_instr_i.result; - + assign pc_o = commit_instr_i.pc; // commit instruction // write register file always_comb begin : commit diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv index cf9cafdb9..be45fc72c 100644 --- a/src/csr_regfile.sv +++ b/src/csr_regfile.sv @@ -32,7 +32,7 @@ module csr_regfile #( // we are taking an exception input exception ex_i, - input fu_op [1:0] csr_op_i, + input fu_op csr_op_i, input logic [11:0] csr_addr_i, input logic [63:0] csr_wdata_i, output logic [63:0] csr_rdata_o, @@ -45,9 +45,6 @@ module csr_regfile #( output logic [31:0] epc_o, output logic [31:0] trap_vector_base_o, output priv_lvl_t priv_lvl_o, - input logic [63:0] badaddr_i, - input logic [63:0] exc_cause_i, - input logic save_exc_cause_i, // MMU output logic enable_translation_o, output logic flag_pum_o, @@ -205,10 +202,10 @@ module csr_regfile #( mstatus_n = csr_wdata; // hardwired zero registers mstatus_n.sd = 1'b0; - mstatus.xs = 2'b0; - mstatus.fs = 2'b0; - mstatus.upie = 1'b0; - mstatus.uie = 1'b0; + mstatus_n.xs = 2'b0; + mstatus_n.fs = 2'b0; + mstatus_n.upie = 1'b0; + mstatus_n.uie = 1'b0; end // machine exception delegation register // 0 - 12 exceptions supported diff --git a/src/ex_stage.sv b/src/ex_stage.sv index c5fa8985e..c78f76dc3 100644 --- a/src/ex_stage.sv +++ b/src/ex_stage.sv @@ -121,7 +121,7 @@ module ex_stage #( // ----- // CSR // ----- - + // CSR address buffer csr_buffer csr_buffer_i ( .commit_i ( csr_commit_i ), .*