diff --git a/src/mem_arbiter.sv b/src/mem_arbiter.sv index f4b9f8b3c..3b00717b8 100644 --- a/src/mem_arbiter.sv +++ b/src/mem_arbiter.sv @@ -51,7 +51,7 @@ module mem_arbiter #( input logic [NR_PORTS-1:0] data_req_i, input logic [NR_PORTS-1:0] data_we_i, input logic [NR_PORTS-1:0][7:0] data_be_i, - input logic [1:0] data_tag_status_i, + input logic [NR_PORTS-1:0][1:0] data_tag_status_i, output logic [NR_PORTS-1:0] data_gnt_o, output logic [NR_PORTS-1:0] data_rvalid_o, output logic [NR_PORTS-1:0][63:0] data_rdata_o @@ -98,19 +98,13 @@ module mem_arbiter #( // addressing read and full write always_comb begin : read_req_write - automatic logic [DATA_WIDTH-1:0] request_index; - // pass through all signals from the correct slave port - address_o = address_i[request_index]; + automatic logic [DATA_WIDTH-1:0] request_index = 0; data_req_o = 1'b0; - data_wdata_o = data_wdata_i[request_index]; - data_be_o = data_be_i[request_index]; - data_we_o = data_we_i[request_index]; - data_tag_status_o = data_tag_status_i[request_index]; - data_gnt_o[request_index] = data_gnt_i; in_data = '{default: 0}; push = 1'b0; request_port_n = request_port_q; + NS = CS; for (int i = 0; i < NR_PORTS; i++) data_gnt_o[i] = 1'b0; @@ -216,6 +210,14 @@ module mem_arbiter #( end default : /* default */; endcase + // pass through all signals from the correct slave port + address_o = address_i[request_index]; + data_wdata_o = data_wdata_i[request_index]; + data_be_o = data_be_i[request_index]; + data_we_o = data_we_i[request_index]; + data_tag_status_o = data_tag_status_i[request_index]; + data_gnt_o[request_index] = data_gnt_i; + // if we got a flush and we are not ready for the flush wait and for it and don't accept any incoming data // e.g.: jump to the flush wait state if (flush_i && !flush_ready) diff --git a/tb/mem_arbiter_tb.sv b/tb/mem_arbiter_tb.sv index 8e3ed33ab..195f426f7 100644 --- a/tb/mem_arbiter_tb.sv +++ b/tb/mem_arbiter_tb.sv @@ -38,27 +38,29 @@ module mem_arbiter_tb; // assign data_gnt = data_gnt_driver & data_req; mem_arbiter dut ( - .clk_i ( clk ), - .rst_ni ( rst_ni ), - .flush_ready_o ( flush_ready_o ), + .clk_i ( clk ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), - .address_o ( slave.address ), - .data_wdata_o ( slave.data_wdata ), - .data_req_o ( slave.data_req ), - .data_we_o ( slave.data_we ), - .data_be_o ( slave.data_be ), - .data_gnt_i ( slave.data_req & slave.data_gnt ), - .data_rvalid_i ( slave.data_rvalid ), - .data_rdata_i ( slave.data_rdata ), + .address_o ( slave.address ), + .data_wdata_o ( slave.data_wdata ), + .data_req_o ( slave.data_req ), + .data_we_o ( slave.data_we ), + .data_be_o ( slave.data_be ), + .data_tag_status_o ( ), + .data_gnt_i ( slave.data_req & slave.data_gnt ), + .data_rvalid_i ( slave.data_rvalid ), + .data_rdata_i ( slave.data_rdata ), - .address_i ( {master[2].address, master[1].address, master[0].address} ), - .data_wdata_i ( {master[2].data_wdata, master[1].data_wdata, master[0].data_wdata} ), - .data_req_i ( {master[2].data_req, master[1].data_req, master[0].data_req} ), - .data_we_i ( {master[2].data_we, master[1].data_we, master[0].data_we} ), - .data_be_i ( {master[2].data_be, master[1].data_be, master[0].data_be} ), - .data_gnt_o ( {master[2].data_gnt, master[1].data_gnt, master[0].data_gnt} ), - .data_rvalid_o ( {master[2].data_rvalid, master[1].data_rvalid, master[0].data_rvalid} ), - .data_rdata_o ( {master[2].data_rdata, master[1].data_rdata, master[0].data_rdata} ) + .address_i ( {master[2].address, master[1].address, master[0].address} ), + .data_wdata_i ( {master[2].data_wdata, master[1].data_wdata, master[0].data_wdata} ), + .data_req_i ( {master[2].data_req, master[1].data_req, master[0].data_req} ), + .data_we_i ( {master[2].data_we, master[1].data_we, master[0].data_we} ), + .data_be_i ( {master[2].data_be, master[1].data_be, master[0].data_be} ), + .data_tag_status_i ( {2'b01, 2'b01, 2'b01 } ), + .data_gnt_o ( {master[2].data_gnt, master[1].data_gnt, master[0].data_gnt} ), + .data_rvalid_o ( {master[2].data_rvalid, master[1].data_rvalid, master[0].data_rvalid} ), + .data_rdata_o ( {master[2].data_rdata, master[1].data_rdata, master[0].data_rdata} ) ); initial begin diff --git a/tb/wave/wave_mem_arbiter.do b/tb/wave/wave_mem_arbiter.do index fb3394628..d5cbe5476 100644 --- a/tb/wave/wave_mem_arbiter.do +++ b/tb/wave/wave_mem_arbiter.do @@ -1,48 +1,8 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate /mem_arbiter_tb/dut/clk_i -add wave -noupdate /mem_arbiter_tb/dut/rst_ni -add wave -noupdate /mem_arbiter_tb/dut/flush_ready_o -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/address_o -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_wdata_o -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_req_o -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_we_o -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_be_o -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_gnt_i -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_rvalid_i -add wave -noupdate -expand -group Slave /mem_arbiter_tb/dut/data_rdata_i -add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/address_i -add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/data_wdata_i -add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_req_i -add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/data_we_i -add wave -noupdate -expand -group Master /mem_arbiter_tb/dut/data_be_i -add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_gnt_o -add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_rvalid_o -add wave -noupdate -expand -group Master -expand /mem_arbiter_tb/dut/data_rdata_o -add wave -noupdate /mem_arbiter_tb/dut/full_o -add wave -noupdate /mem_arbiter_tb/dut/empty_o -add wave -noupdate /mem_arbiter_tb/dut/data_i -add wave -noupdate /mem_arbiter_tb/dut/push_i -add wave -noupdate /mem_arbiter_tb/dut/data_o -add wave -noupdate /mem_arbiter_tb/dut/pop_i -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/clk_i -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/rst_ni -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/flush_i -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/full_o -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/empty_o -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/single_element_o -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/data_i -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/push_i -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/data_o -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/pop_i -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/read_pointer_n -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/read_pointer_q -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/write_pointer_n -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/write_pointer_q -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/status_cnt_n -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/status_cnt_q -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/mem_n -add wave -noupdate -expand -group FIFO /mem_arbiter_tb/dut/fifo_i/mem_q +add wave -noupdate /mem_arbiter_tb/dut/* + +add wave -noupdate -group FIFO /mem_arbiter_tb/dut/fifo_i/* TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {421 ns} 0} quietly wave cursor active 1