diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv
index cf6ee1521..0d309a58c 100644
--- a/core/cvxif_fu.sv
+++ b/core/cvxif_fu.sv
@@ -22,6 +22,8 @@ module cvxif_fu
     input  logic                                   clk_i,
     // Asynchronous reset active low - SUBSYSTEM
     input  logic                                   rst_ni,
+    // Virtualization mode state - CSR_REGFILE
+    input  logic                                   v_i,
     // CVXIF instruction is valid - ISSUE_STAGE
     input  logic                                   x_valid_i,
     // Transaction ID - ISSUE_STAGE
@@ -68,6 +70,10 @@ module cvxif_fu
     x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0;
     if (CVA6Cfg.TvalEn)
       x_exception_o.tval = x_off_instr_i;  // TODO Optimization : Set exception in IRO.
+    // Hypervisor exception fields
+    x_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}};
+    x_exception_o.tinst = '0;
+    x_exception_o.gva   = CVA6Cfg.RVH ? v_i : 1'b0;
   end
 
 endmodule
diff --git a/core/ex_stage.sv b/core/ex_stage.sv
index 84f536971..74cad5fb9 100644
--- a/core/ex_stage.sv
+++ b/core/ex_stage.sv
@@ -621,6 +621,7 @@ module ex_stage
     ) cvxif_fu_i (
         .clk_i,
         .rst_ni,
+        .v_i,
         .x_valid_i(|x_valid_i),
         .x_trans_id_i(cvxif_data.trans_id),
         .x_illegal_i(x_transaction_rejected_i),