diff --git a/core/cva6.sv b/core/cva6.sv index 0d3a9c00e..3161c5c62 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -261,6 +261,7 @@ module cva6 import ariane_pkg::*; #( logic dcache_commit_wbuffer_not_ni; logic [riscv::VLEN-1:0] lsu_addr; + logic [riscv::PLEN-1:0] mem_paddr; logic [(riscv::XLEN/8)-1:0] lsu_rmask; logic [(riscv::XLEN/8)-1:0] lsu_wmask; logic [ariane_pkg::TRANS_ID_BITS-1:0] lsu_addr_trans_id; @@ -509,6 +510,7 @@ module cva6 import ariane_pkg::*; #( .pmpaddr_i ( pmpaddr ), //RVFI .lsu_addr_o ( lsu_addr ), + .mem_paddr_o ( mem_paddr ), .lsu_rmask_o ( lsu_rmask ), .lsu_wmask_o ( lsu_wmask ), .lsu_addr_trans_id_o ( lsu_addr_trans_id ) @@ -1012,6 +1014,8 @@ module cva6 import ariane_pkg::*; #( rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc; `ifdef RVFI_MEM rvfi_o[i].mem_addr = commit_instr_id_commit[i].lsu_addr; + // So far, only write paddr is reported. TODO: read paddr + rvfi_o[i].mem_paddr = mem_paddr; rvfi_o[i].mem_wmask = commit_instr_id_commit[i].lsu_wmask; rvfi_o[i].mem_wdata = commit_instr_id_commit[i].lsu_wdata; rvfi_o[i].mem_rmask = commit_instr_id_commit[i].lsu_rmask; diff --git a/core/ex_stage.sv b/core/ex_stage.sv index e526055cb..202047178 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -120,6 +120,7 @@ module ex_stage import ariane_pkg::*; #( // RVFI output [riscv::VLEN-1:0] lsu_addr_o, + output [riscv::PLEN-1:0] mem_paddr_o, output [(riscv::XLEN/8)-1:0] lsu_rmask_o, output [(riscv::XLEN/8)-1:0] lsu_wmask_o, output [ariane_pkg::TRANS_ID_BITS-1:0] lsu_addr_trans_id_o @@ -335,6 +336,7 @@ module ex_stage import ariane_pkg::*; #( .pmpcfg_i, .pmpaddr_i, .lsu_addr_o, + .mem_paddr_o, .lsu_rmask_o, .lsu_wmask_o, .lsu_addr_trans_id_o @@ -366,10 +368,10 @@ module ex_stage import ariane_pkg::*; #( assign x_valid_o = '0; end - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin current_instruction_is_sfence_vma <= 1'b0; - end else begin + end else begin if (flush_i) begin current_instruction_is_sfence_vma <= 1'b0; end else if ((fu_data_i.operator == SFENCE_VMA) && csr_valid_i) begin @@ -379,15 +381,15 @@ module ex_stage import ariane_pkg::*; #( end // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction. - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - asid_to_be_flushed <= '0; - vaddr_to_be_flushed <= '0; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + asid_to_be_flushed <= '0; + vaddr_to_be_flushed <= '0; // if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen - end else if ((~current_instruction_is_sfence_vma) && (~((fu_data_i.operator == SFENCE_VMA) && csr_valid_i))) begin - vaddr_to_be_flushed <= rs1_forwarding_i; - asid_to_be_flushed <= rs2_forwarding_i[ASID_WIDTH-1:0]; - end - end + end else if ((~current_instruction_is_sfence_vma) && (~((fu_data_i.operator == SFENCE_VMA) && csr_valid_i))) begin + vaddr_to_be_flushed <= rs1_forwarding_i; + asid_to_be_flushed <= rs2_forwarding_i[ASID_WIDTH-1:0]; + end + end endmodule diff --git a/core/include/ariane_rvfi_pkg.sv b/core/include/ariane_rvfi_pkg.sv index 707f3f107..d72a447fe 100644 --- a/core/include/ariane_rvfi_pkg.sv +++ b/core/include/ariane_rvfi_pkg.sv @@ -32,7 +32,8 @@ package ariane_rvfi_pkg; logic [NRET*riscv::XLEN-1:0] pc_rdata; logic [NRET*riscv::XLEN-1:0] pc_wdata; - logic [NRET*riscv::XLEN-1:0] mem_addr; + logic [NRET*riscv::VLEN-1:0] mem_addr; + logic [NRET*riscv::PLEN-1:0] mem_paddr; logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask; logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask; logic [NRET*riscv::XLEN-1:0] mem_rdata; diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index b64c43a6a..51872b58d 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -75,6 +75,7 @@ module load_store_unit import ariane_pkg::*; #( //RVFI output [riscv::VLEN-1:0] lsu_addr_o, + output [riscv::PLEN-1:0] mem_paddr_o, output [(riscv::XLEN/8)-1:0] lsu_rmask_o, output [(riscv::XLEN/8)-1:0] lsu_wmask_o, output [ariane_pkg::TRANS_ID_BITS-1:0] lsu_addr_trans_id_o @@ -253,6 +254,7 @@ module load_store_unit import ariane_pkg::*; #( // MMU port .translation_req_o ( st_translation_req ), .vaddr_o ( st_vaddr ), + .mem_paddr_o ( mem_paddr_o ), .paddr_i ( mmu_paddr ), .ex_i ( mmu_exception ), .dtlb_hit_i ( dtlb_hit ), diff --git a/core/store_buffer.sv b/core/store_buffer.sv index 66633292d..bd018139d 100644 --- a/core/store_buffer.sv +++ b/core/store_buffer.sv @@ -34,6 +34,7 @@ module store_buffer import ariane_pkg::*; ( input logic valid_without_flush_i, // just tell if the address is valid which we are current putting and do not take any further action input logic [riscv::PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue + output [riscv::PLEN-1:0] mem_paddr_o, input riscv::xlen_t data_i, // data which is placed in the queue input logic [(riscv::XLEN/8)-1:0] be_i, // byte enable in input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) @@ -137,6 +138,8 @@ module store_buffer import ariane_pkg::*; ( assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be; assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size; + assign mem_paddr_o = commit_queue_n[commit_read_pointer_n].address; + always_comb begin : store_if automatic logic [DEPTH_COMMIT:0] commit_status_cnt; commit_status_cnt = commit_status_cnt_q; diff --git a/core/store_unit.sv b/core/store_unit.sv index c485ec366..e6b5204ea 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -34,6 +34,7 @@ module store_unit import ariane_pkg::*; ( // MMU -> Address Translation output logic translation_req_o, // request address translation output logic [riscv::VLEN-1:0] vaddr_o, // virtual address out + output [riscv::PLEN-1:0] mem_paddr_o, input logic [riscv::PLEN-1:0] paddr_i, // physical address in input exception_t ex_i, input logic dtlb_hit_i, // will be one in the same cycle translation_req was asserted if it hits @@ -231,6 +232,7 @@ module store_unit import ariane_pkg::*; ( // the whole pipeline anyway .valid_without_flush_i ( st_valid_without_flush ), .paddr_i, + .mem_paddr_o ( mem_paddr_o ), .data_i ( st_data_q ), .be_i ( st_be_q ), .data_size_i ( st_data_size_q ), diff --git a/corev_apu/tb/rvfi_pkg.sv b/corev_apu/tb/rvfi_pkg.sv index 21733585e..c0b6c973a 100644 --- a/corev_apu/tb/rvfi_pkg.sv +++ b/corev_apu/tb/rvfi_pkg.sv @@ -32,7 +32,8 @@ package rvfi_pkg; logic [NRET*riscv::XLEN-1:0] pc_rdata; logic [NRET*riscv::XLEN-1:0] pc_wdata; - logic [NRET*riscv::XLEN-1:0] mem_addr; + logic [NRET*riscv::VLEN-1:0] mem_addr; + logic [NRET*riscv::PLEN-1:0] mem_paddr; logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask; logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask; logic [NRET*riscv::XLEN-1:0] mem_rdata;