diff --git a/src/ariane.sv b/src/ariane.sv index 1619946e1..b0eb6fe69 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -41,7 +41,7 @@ module ariane // Instruction memory interface output logic [63:0] instr_if_address_o, output logic instr_if_data_req_o, - output logic [7:0] instr_if_data_be_o, + output logic [3:0] instr_if_data_be_o, input logic instr_if_data_gnt_i, input logic instr_if_data_rvalid_i, input logic [31:0] instr_if_data_rdata_i, @@ -318,7 +318,6 @@ module ariane // Commit // --------- commit_stage commit_stage_i ( - .priv_lvl_o ( priv_lvl ), .exception_o ( ex_commit_csr ), .commit_instr_i ( commit_instr_id_commit ), .commit_ack_o ( commit_ack_commit_id ), diff --git a/src/commit_stage.sv b/src/commit_stage.sv index ab330530e..1ddd18703 100644 --- a/src/commit_stage.sv +++ b/src/commit_stage.sv @@ -22,7 +22,6 @@ module commit_stage ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - output priv_lvl_t priv_lvl_o, // privilege level out output exception exception_o, // take exception to controller // from scoreboard @@ -38,7 +37,7 @@ module commit_stage ( output logic [63:0] pc_o, output fu_op csr_op_o, output logic [63:0] csr_wdata_o, - output logic [63:0] csr_rdata_i, + input logic [63:0] csr_rdata_i, input exception csr_exception_i, // to ex output logic commit_lsu_o, @@ -104,9 +103,16 @@ module commit_stage ( // here we know for sure that we are taking the exception always_comb begin : exception_handling exception_o.valid = 1'b0; - if (commit_instr_i.ex.valid || csr_exception_i.valid) begin - // check for CSR exception - exception_o.valid = 1'b1; + exception_o.cause = 64'b0; + exception_o.tval = 64'b0; + // check for CSR exception + if (csr_exception_i.valid) begin + exception_o = csr_exception_i; end + // but we give precedence to exceptions which happened earlier + if (commit_instr_i.ex.valid) begin + exception_o = commit_instr_i.ex; + end + end endmodule \ No newline at end of file diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv index 4cddf680c..3073df8f3 100644 --- a/src/csr_regfile.sv +++ b/src/csr_regfile.sv @@ -61,7 +61,7 @@ module csr_regfile #( // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception; - logic csr_we; + logic csr_we, csr_read; logic [63:0] csr_wdata, csr_rdata; // ---------------- // CSR Registers @@ -125,39 +125,41 @@ module csr_regfile #( // ---------------- // CSR Read logic // ---------------- - always_comb begin : csr_read + always_comb begin : csr_read_process // a read access exception can only occur if we attempt to read a CSR which does not exist read_access_exception = 1'b0; csr_rdata = 64'b0; - case (csr_addr.address) + if (csr_read) begin + case (csr_addr.address) - CSR_SSTATUS: csr_rdata = mstatus_q & 64'h3fffe1fee; - CSR_SIE: csr_rdata = mie_q & mideleg_q; - CSR_SIP: csr_rdata = mip_q & mideleg_q; - CSR_STVEC: csr_rdata = stvec_q; - CSR_SSCRATCH: csr_rdata = sscratch_q; - CSR_SEPC: csr_rdata = sepc_q; - CSR_SCAUSE: csr_rdata = scause_q; - CSR_STVAL: csr_rdata = stval_q; - CSR_SATP: csr_rdata = satp_q; + CSR_SSTATUS: csr_rdata = mstatus_q & 64'h3fffe1fee; + CSR_SIE: csr_rdata = mie_q & mideleg_q; + CSR_SIP: csr_rdata = mip_q & mideleg_q; + CSR_STVEC: csr_rdata = stvec_q; + CSR_SSCRATCH: csr_rdata = sscratch_q; + CSR_SEPC: csr_rdata = sepc_q; + CSR_SCAUSE: csr_rdata = scause_q; + CSR_STVAL: csr_rdata = stval_q; + CSR_SATP: csr_rdata = satp_q; - CSR_MSTATUS: csr_rdata = mstatus_q; - CSR_MISA: csr_rdata = ISA_CODE; - CSR_MEDELEG: csr_rdata = medeleg_q; - CSR_MIDELEG: csr_rdata = mideleg_q; - CSR_MIP: csr_rdata = mip_q; - CSR_MIE: csr_rdata = mie_q; - CSR_MTVEC: csr_rdata = mtvec_q; - CSR_MSCRATCH: csr_rdata = mscratch_q; - CSR_MEPC: csr_rdata = mepc_q; - CSR_MCAUSE: csr_rdata = mcause_q; - CSR_MTVAL: csr_rdata = mtval_q; - CSR_MVENDORID: csr_rdata = 64'b0; // not implemented - CSR_MARCHID: csr_rdata = 64'b0; // PULP, anonymous source (no allocated ID yet) - CSR_MIMPID: csr_rdata = 64'b0; // not implemented - CSR_MHARTID: csr_rdata = {53'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]}; - default: read_access_exception = 1'b1; - endcase + CSR_MSTATUS: csr_rdata = mstatus_q; + CSR_MISA: csr_rdata = ISA_CODE; + CSR_MEDELEG: csr_rdata = medeleg_q; + CSR_MIDELEG: csr_rdata = mideleg_q; + CSR_MIP: csr_rdata = mip_q; + CSR_MIE: csr_rdata = mie_q; + CSR_MTVEC: csr_rdata = mtvec_q; + CSR_MSCRATCH: csr_rdata = mscratch_q; + CSR_MEPC: csr_rdata = mepc_q; + CSR_MCAUSE: csr_rdata = mcause_q; + CSR_MTVAL: csr_rdata = mtval_q; + CSR_MVENDORID: csr_rdata = 64'b0; // not implemented + CSR_MARCHID: csr_rdata = 64'b0; // PULP, anonymous source (no allocated ID yet) + CSR_MIMPID: csr_rdata = 64'b0; // not implemented + CSR_MHARTID: csr_rdata = {53'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]}; + default: read_access_exception = 1'b1; + endcase + end end // --------------------------- // CSR Write and update logic @@ -238,7 +240,7 @@ module csr_regfile #( // update exception CSRs // we got an exception update cause, pc and stval register if (ex_i.valid) begin - automatic priv_lvl_t trap_to_priv_lvl; + automatic priv_lvl_t trap_to_priv_lvl = PRIV_LVL_M; // figure out where to trap to // a m-mode trap might be delegated // first figure out if this was an exception or an interrupt e.g.: look at bit 63 @@ -280,12 +282,16 @@ module csr_regfile #( always_comb begin : csr_op_logic csr_wdata = csr_wdata_i; csr_we = 1'b1; - + csr_read = 1'b1; unique case (csr_op_i) CSR_WRITE: csr_wdata = csr_wdata_i; CSR_SET: csr_wdata = csr_wdata_i | csr_rdata; CSR_CLEAR: csr_wdata = (~csr_wdata_i) & csr_rdata; - default: csr_we = 1'b0; + CSR_READ: csr_we = 1'b0; + default: begin + csr_we = 1'b0; + csr_read = 1'b0; + end endcase end // ------------------- @@ -345,6 +351,8 @@ module csr_regfile #( mtvec_q <= {boot_addr_i[63:2], 2'b0}; // set to boot address + direct mode medeleg_q <= 64'b0; mideleg_q <= 64'b0; + mip_q <= 64'b0; + mie_q <= 64'b0; mepc_q <= 64'b0; mcause_q <= 64'b0; mscratch_q <= 64'b0; @@ -358,7 +366,7 @@ module csr_regfile #( satp_q <= 64'b0; end else begin priv_lvl_q <= priv_lvl_n; - prev_priv_lvl_q <= prev_priv_lvl_n; + prev_priv_lvl_q <= priv_lvl_q; // machine mode registers mstatus_q <= mstatus_n; mtvec_q <= mtvec_n; diff --git a/src/ex_stage.sv b/src/ex_stage.sv index c78f76dc3..0a40f0d4f 100644 --- a/src/ex_stage.sv +++ b/src/ex_stage.sv @@ -72,7 +72,7 @@ module ex_stage #( output logic [63:0] instr_if_address_o, output logic instr_if_data_req_o, - output logic [7:0] instr_if_data_be_o, + output logic [3:0] instr_if_data_be_o, input logic instr_if_data_gnt_i, input logic instr_if_data_rvalid_i, input logic [31:0] instr_if_data_rdata_i, diff --git a/src/lsu.sv b/src/lsu.sv index 821fbfc63..6ec80f70b 100644 --- a/src/lsu.sv +++ b/src/lsu.sv @@ -55,7 +55,7 @@ module lsu #( // Instruction memory/cache output logic [63:0] instr_if_address_o, output logic instr_if_data_req_o, - output logic [7:0] instr_if_data_be_o, + output logic [3:0] instr_if_data_be_o, input logic instr_if_data_gnt_i, input logic instr_if_data_rvalid_i, input logic [31:0] instr_if_data_rdata_i, diff --git a/src/mmu.sv b/src/mmu.sv index 840cc55e3..9ddfb83d8 100644 --- a/src/mmu.sv +++ b/src/mmu.sv @@ -57,7 +57,7 @@ module mmu #( // Instruction memory/cache output logic [63:0] instr_if_address_o, output logic instr_if_data_req_o, - output logic [7:0] instr_if_data_be_o, + output logic [3:0] instr_if_data_be_o, input logic instr_if_data_gnt_i, input logic instr_if_data_rvalid_i, input logic [31:0] instr_if_data_rdata_i, diff --git a/tb/wave/wave_core.do b/tb/wave/wave_core.do index 83bd3f5aa..948cd5a08 100644 --- a/tb/wave/wave_core.do +++ b/tb/wave/wave_core.do @@ -10,7 +10,6 @@ add wave -noupdate -group instr_if /core_tb/instr_if/data_rdata add wave -noupdate -group instr_if /core_tb/instr_if/data_we add wave -noupdate -group instr_if /core_tb/instr_if/data_be add wave -noupdate -group Core /core_tb/dut/clk_i -add wave -noupdate -group Core /core_tb/dut/rst_n add wave -noupdate -group Core /core_tb/dut/clock_en_i add wave -noupdate -group Core /core_tb/dut/test_en_i add wave -noupdate -group Core /core_tb/dut/fetch_enable_i @@ -24,64 +23,97 @@ add wave -noupdate -group Core /core_tb/dut/irq_id_i add wave -noupdate -group Core /core_tb/dut/irq_ack_o add wave -noupdate -group Core /core_tb/dut/irq_sec_i add wave -noupdate -group Core /core_tb/dut/sec_lvl_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/clk_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/rst_ni -add wave -noupdate -group if /core_tb/dut/i_if_stage/req_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/if_busy_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/id_ready_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/halt_if_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_req_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_addr_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_gnt_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rvalid_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rdata_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_valid_id_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rdata_id_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/is_compressed_id_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/illegal_c_insn_id_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/pc_if_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/pc_id_o -add wave -noupdate -group if /core_tb/dut/i_if_stage/boot_addr_i -add wave -noupdate -group if /core_tb/dut/i_if_stage/if_ready -add wave -noupdate -group if /core_tb/dut/i_if_stage/if_valid -add wave -noupdate -group if /core_tb/dut/i_if_stage/branch_req -add wave -noupdate -group if /core_tb/dut/i_if_stage/valid -add wave -noupdate -group if /core_tb/dut/i_if_stage/prefetch_busy -add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_addr_n -add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_valid -add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_ready -add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_rdata -add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_addr -add wave -noupdate -group if /core_tb/dut/i_if_stage/offset_fsm_cs -add wave -noupdate -group if /core_tb/dut/i_if_stage/offset_fsm_ns -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_decompressed -add wave -noupdate -group if /core_tb/dut/i_if_stage/illegal_c_insn -add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_compressed_int -add wave -noupdate -group if /core_tb/dut/i_if_stage/clear_instr_valid_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/clk -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/rst_n -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/req_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/branch_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/ready_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/valid_o -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_o -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/rdata_o -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_req_o -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_gnt_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_addr_o -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_rdata_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_rvalid_i -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/busy_o -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/CS -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/NS -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_addr_q -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fetch_addr -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_valid -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_valid -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_ready -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_clear -add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/valid_stored +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/clk +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/rst_n +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/clear_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/in_addr_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/in_rdata_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/in_valid_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/in_ready_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/out_addr_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/out_rdata_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/out_valid_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/out_ready_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/out_valid_stored_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/addr_n +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/addr_int +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/addr_Q +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/rdata_n +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/rdata_int +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/rdata_Q +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/valid_n +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/valid_int +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/valid_Q +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/addr_next +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/rdata +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/rdata_unaligned +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/valid +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/valid_unaligned +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/aligned_is_compressed +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/unaligned_is_compressed +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/aligned_is_compressed_st +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/unaligned_is_compressed_st +add wave -noupdate -expand -group if_stage -group prefetch_buffer -group fifo /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_i/j +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/clk +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/rst_n +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/req_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/branch_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/addr_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/ready_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/valid_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/addr_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/rdata_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/instr_req_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/instr_gnt_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/instr_addr_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/instr_rdata_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/instr_rvalid_i +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/busy_o +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/CS +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/NS +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/instr_addr_q +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/fetch_addr +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/addr_valid +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_valid +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_ready +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/fifo_clear +add wave -noupdate -expand -group if_stage -group prefetch_buffer /core_tb/dut/if_stage_i/prefetch_buffer_i/valid_stored +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/clk_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/rst_ni +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/flush_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/req_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/if_busy_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/id_ready_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/halt_if_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_req_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_addr_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_gnt_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_rvalid_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_rdata_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_valid_id_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_rdata_id_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/is_compressed_id_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/illegal_c_insn_id_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/pc_if_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/pc_id_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/ex_o +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/boot_addr_i +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/if_ready +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/if_valid +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/branch_req +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/valid +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/prefetch_busy +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/fetch_addr_n +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/fetch_valid +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/fetch_ready +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/fetch_rdata +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/fetch_addr +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/offset_fsm_cs +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/offset_fsm_ns +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_decompressed +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/illegal_c_insn +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/instr_compressed_int +add wave -noupdate -expand -group if_stage /core_tb/dut/if_stage_i/clear_instr_valid_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/clk_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rst_ni add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/test_en_i @@ -89,7 +121,6 @@ add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/flush_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/instruction_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/instruction_valid_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/pc_if_i -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/ex_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/ready_o add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operator_o add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operand_a_o @@ -107,135 +138,333 @@ add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wb_valid_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/waddr_a_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wdata_a_i add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/we_a_i -add wave -noupdate -expand -group id_stage -expand /core_tb/dut/id_stage_i/commit_instr_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/commit_instr_o add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/commit_ack_i -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/full_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rd_clobber_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_i -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_valid_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_i -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_valid_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_instr_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/decoded_instr_i -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_instr_valid_o -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_ack_i -add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/illegal_instr_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/clk_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/rst_ni -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operator_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operand_a_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operand_b_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/trans_id_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_ready_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_result_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_trans_id_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/comparison_result_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/lsu_ready_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/lsu_valid_i -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/mult_ready_o -add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/mult_valid_i -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/clk_i -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/rst_ni -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/pc_i -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_i -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/ex_i -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_o -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/illegal_instr_o -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instr -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_select -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_i_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_iz_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_sb_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_u_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_uj_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_z_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s2_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_bi_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s3_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vs_type -add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vu_type -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operator_i -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_i -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_i -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_o -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_ext_o -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/result_o -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/comparison_result_o -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal_result_o -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev32 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_neg -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_op_b_negate -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_a -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_b -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_arithmetic -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_amt -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a32 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result32 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result32 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result32 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_64 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_32 -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_greater_equal -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_signed -add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_result -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/clk_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rst_ni -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/test_en_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/flush_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_valid_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_ack_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_valid_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_valid_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rd_clobber_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_ready_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_ready_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_valid_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_ready_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_valid_o -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/waddr_a_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/wdata_a_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/we_a_i -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/stall -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/fu_busy -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_regfile -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_regfile -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_n -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_q -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_n -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_q -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_n -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_q -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_n -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_q -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_n -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_q -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs1 -add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs2 +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/clk_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rst_ni +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/full_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/flush_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rd_clobber_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rs1_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rs1_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rs1_valid_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rs2_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rs2_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/rs2_valid_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/commit_instr_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/commit_ack_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/decoded_instr_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/decoded_instr_valid_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/issue_instr_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/issue_instr_valid_o +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/issue_ack_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/trans_id_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/wdata_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/ex_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/wb_valid_i +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/mem_q +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/mem_n +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/issue_pointer_n +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/issue_pointer_q +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/commit_pointer_n +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/commit_pointer_q +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/top_pointer_n +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/top_pointer_q +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/top_pointer_qq +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/pointer_overflow +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/empty +add wave -noupdate -expand -group id_stage -expand -group scoreboard /core_tb/dut/id_stage_i/scoreboard_i/reset_condition +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/clk_i +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/rst_ni +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/pc_i +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_i +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/ex_i +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_o +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/instr +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_select +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_i_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_iz_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_sb_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_u_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_uj_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_z_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s2_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_bi_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s3_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vs_type +add wave -noupdate -expand -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vu_type +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/clk_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rst_ni +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/test_en_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/flush_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_valid_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_ack_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_valid_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_valid_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rd_clobber_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_ready_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_ready_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_valid_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_ready_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_valid_o +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/waddr_a_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/wdata_a_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/we_a_i +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/stall +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/fu_busy +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_regfile +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_regfile +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_n +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_q +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_n +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_q +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_n +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_q +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_n +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_q +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_n +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_q +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs1 +add wave -noupdate -expand -group id_stage -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs2 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/operator_i +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_i +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_i +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_o +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_ext_o +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/result_o +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/comparison_result_o +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal_result_o +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev32 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_neg +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_op_b_negate +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_a +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_b +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_arithmetic +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_amt +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a32 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result32 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result32 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result32 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_64 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_32 +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/is_greater_equal +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_signed +add wave -noupdate -group ex_stage -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_result +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/clk_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/rst_ni +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/flush_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/operator_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/operand_a_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/operand_b_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/imm_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/lsu_ready_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/lsu_valid_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/trans_id_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/lsu_trans_id_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/lsu_result_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/lsu_valid_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/commit_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/enable_translation_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/fetch_req_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/fetch_gnt_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/fetch_valid_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/fetch_err_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/fetch_vaddr_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/fetch_rdata_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/priv_lvl_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/flag_pum_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/flag_mxr_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/pd_ppn_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/asid_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/flush_tlb_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/instr_if_address_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/instr_if_data_req_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/instr_if_data_be_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/instr_if_data_gnt_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/instr_if_data_rvalid_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/instr_if_data_rdata_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_address_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_wdata_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_req_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_we_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_be_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_gnt_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_rvalid_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_if_data_rdata_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/lsu_exception_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_misaligned +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/CS +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/NS +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/vaddr_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/stall +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/get_from_register +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/vaddr +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/be +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/operator +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/trans_id +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/vaddr_q +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_q +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/operator_q +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/trans_id_q +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/st_buffer_paddr +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/st_buffer_data +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/st_buffer_be +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/st_buffer_valid +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/st_ready +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/st_valid +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/translation_req +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/translation_valid +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/paddr_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/address_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_wdata_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_req_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_we_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_be_i +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_gnt_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_rvalid_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/data_rdata_o +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/rdata +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/address_match +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/op +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/rdata_d_ext +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/rdata_w_ext +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/rdata_h_ext +add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/rdata_b_ext +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/clk_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/rst_ni +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/flush_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/operator_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/operand_a_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/operand_b_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/trans_id_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_ready_o +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_valid_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_trans_id_o +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_result_o +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_valid_o +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/commit_i +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_addr_o +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_reg_n +add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/csr_reg_q +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/clk_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/rst_ni +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/operator_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/operand_a_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/operand_b_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/trans_id_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/alu_ready_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/alu_result_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/alu_trans_id_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/comparison_result_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/lsu_ready_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/lsu_valid_i +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/mult_ready_o +add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/mult_valid_i +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/clk_i +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/rst_ni +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/exception_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/commit_instr_i +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/commit_ack_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/waddr_a_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/wdata_a_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/we_a_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/pc_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/csr_op_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/csr_wdata_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/csr_rdata_i +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/csr_exception_i +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/commit_lsu_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/commit_csr_o +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/irq_enable_i +add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/exception +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/clk_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/rst_ni +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/flush_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/core_id_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/cluster_id_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/boot_addr_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/ex_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_op_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_addr_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_wdata_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_rdata_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/pc_i +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_exception_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/irq_enable_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/epc_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/trap_vector_base_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/priv_lvl_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/enable_translation_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/flag_pum_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/flag_mxr_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/pd_ppn_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/asid_o +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_addr +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/read_access_exception +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/update_access_exception +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_we +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_wdata +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/csr_rdata +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/priv_lvl_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/priv_lvl_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/prev_priv_lvl_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/prev_priv_lvl_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mstatus_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mstatus_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mtvec_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mtvec_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/medeleg_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/medeleg_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mideleg_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mideleg_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mip_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mip_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mie_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mie_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mscratch_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mscratch_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mepc_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mepc_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mcause_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mcause_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mtval_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/mtval_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/stvec_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/stvec_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/sscratch_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/sscratch_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/sepc_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/sepc_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/scause_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/scause_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/stval_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/stval_n +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/satp_q +add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/satp_n TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {499 ns} 0} {{Cursor 2} {278 ns} 1} +WaveRestoreCursors {{Cursor 1} {207 ns} 0} {{Cursor 2} {278 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 241 configure wave -valuecolwidth 258 @@ -251,4 +480,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {840 ns} +WaveRestoreZoom {0 ns} {1580 ns}