diff --git a/Makefile b/Makefile index 4dedbd991..d2860667c 100644 --- a/Makefile +++ b/Makefile @@ -17,7 +17,7 @@ interfaces = include/debug_if.svh include/mem_if.svh src = alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv \ tb/scoreboard_tb.sv \ if_stage.sv compressed_decoder.sv fetch_fifo.sv commit_stage.sv prefetch_buffer.sv \ - mmu.sv \ + mmu.sv lsu.sv \ scoreboard.sv issue_read_operands.sv decoder.sv id_stage.sv util/cluster_clock_gating.sv regfile.sv ex_stage.sv ariane.sv \ tb/core_tb.sv diff --git a/ariane.sv b/ariane.sv index bf9ecf9ec..49dcf1b32 100644 --- a/ariane.sv +++ b/ariane.sv @@ -113,6 +113,9 @@ module ariane logic flush_tlb_i; logic lsu_ready_wb_i; + logic [63:0] lsu_wdata_i; + logic [63:0] lsu_rdata_o; + assign id_ready_i = 1'b1; assign halt_if_i = 1'b0; @@ -225,6 +228,8 @@ module ariane .lsu_be_i ( lsu_be_i ), .lsu_err_o ( lsu_err_o ), .lsu_vaddr_i ( lsu_vaddr_i ), + .lsu_wdata_i ( lsu_wdata_i ), + .lsu_rdata_o ( lsu_rdata_o ), .priv_lvl_i ( priv_lvl_i ), // from CSR .flag_pum_i ( flag_pum_i ), // from CSR .flag_mxr_i ( flag_mxr_i ), // from CSR diff --git a/docs/architecture.md b/docs/architecture.md index c99de6a2f..8bf736d4d 100644 --- a/docs/architecture.md +++ b/docs/architecture.md @@ -99,16 +99,25 @@ If an exception was signaled by the WB stage, the LSU kills all entries in its s The LSU of the core takes care of accessing the data memory. Load and stores on words (32 bit), half words (16 bit) and bytes (8 bit) are supported. Table 3 describes the signals that are used by the LSU. -| **Signal** | **Direction** | **Description** | -| ------------------ | ------------- | ---------------------------------------------------------------------------------------------------------------------- | -| data_req_o | output | Request ready, must stay high until data_gnt_i is high for one cycle | -| data_addr_o[31:0] | output | Address | -| data_we_o | output | Write Enable, high for writes, low for reads. Sent together with data_req_o | -| data_be_o[3:0] | output | Byte Enable. Is set for the bytes to write/read, sent together with data_req_o | -| data_wdata_o[31:0] | output | Data to be written to memory, sent together with data_req_o | -| data_rdata_i[31:0] | input | Data read from memory | -| data_rvalid_i | input | data_rdata_is holds valid data when data_rvalid_i is high. This signal will be high for exactly one cycle per request. | -| data_gnt_i | input | The other side accepted the request. data_addr_o may change in the next cycle | +| **Signal** | **Direction** | **Description** | +|-----------------|---------------|------------------------------------------------------------------------------------------------------------------------| +| data_req_o | Output | Request ready, must stay high until data_gnt_i is high for one cycle | +| data_addr_o | Output | Address | +| data_we_o | Output | Write Enable, high for writes, low for reads. Sent together with data_req_o | +| data_be_o | Output | Byte Enable. Is set for the bytes to write/read, sent together with data_req_o | +| data_wdata_o | Output | Data to be written to memory, sent together with data_req_o | +| data_rdata_i | Input | Data read from memory | +| data_rvalid_i | Input | data_rdata_is holds valid data when data_rvalid_i is high. This signal will be high for exactly one cycle per request. | +| data_gnt_i | Input | The other side accepted the request. data_addr_o may change in the next cycle | +| operator_i | Input | Operation to perform e.g.: LD/SD/... | +| operand_a_i | Input | Operand a in from scoreboard/issue | +| operand_b_i | Input | Operand b in from scoreboard/issue | +| lsu_ready_o | Output | LSU is ready e.g. not busy and can accept new instructions | +| lsu_valid_i | Input | LSU is requested to perform the instruction given in operator_i | +| lsu_trans_id_i | Input | Transaction ID needed for the correct writeback | +| lsu_trans_id_o | Output | Output to writeback for which it acknowledges the corresponding transaction | +| lsu_valid_o | Output | Output of LSU is valid | +| lsu_exception_o | Output | To writeback, an exception has occured for the following instruction | ## Protocol diff --git a/lsu.sv b/lsu.sv index e69de29bb..27a709118 100644 --- a/lsu.sv +++ b/lsu.sv @@ -0,0 +1,32 @@ +import ariane_pkg::*; + +module lsu ( + input logic clk, + input logic rst_n, + + // output to data memory + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + input logic data_err_i, + + output logic [63:0] data_addr_o, + output logic data_we_o, + output logic [7:0] data_be_o, + output logic [63:0] data_wdata_o, + input logic [63:0] data_rdata_i, + + input fu_op operator_i, + input logic [63:0] operand_a_i, + input logic [63:0] operand_b_i, + output logic lsu_ready_o, // FU is ready e.g. not busy + input logic lsu_valid_i, // Input is valid + input logic lsu_trans_id_i, // transaction id, needed for WB + output logic [4:0] lsu_trans_id_o, // ID of scoreboard entry at which to write back + output logic lsu_valid_o, // transaction id for which the output is the requested one + + output exception lsu_exception_o // to writeback, signal exception status ld/st exception + +); + +endmodule \ No newline at end of file