From b484f5f3ee480068b6af1e038796e4db7a31a240 Mon Sep 17 00:00:00 2001 From: khandelwaltanuj <158037163+khandelwaltanuj@users.noreply.github.com> Date: Tue, 17 Jun 2025 08:00:48 +0200 Subject: [PATCH] dtlb_lu_access is done only when misalgined ex valid is 0 (#2989) This fixes issue #2988 and #2827 --------- Co-authored-by: JeanRochCoulon --- config/gen_from_riscv_config/scripts/libs/utils.py | 6 +++++- core/cva6_mmu/cva6_mmu.sv | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/config/gen_from_riscv_config/scripts/libs/utils.py b/config/gen_from_riscv_config/scripts/libs/utils.py index 796a6057c..93a57452e 100644 --- a/config/gen_from_riscv_config/scripts/libs/utils.py +++ b/config/gen_from_riscv_config/scripts/libs/utils.py @@ -1273,7 +1273,11 @@ class CsrParser: if isinstance(RegElement.get("address", None), str) else hex(RegElement.get("address", None)) ) - reset = hex(RegElement.get("reset-val", "")) + + if RegElement.get("reset-val", "") != "": + reset = hex(RegElement.get("reset-val", "")) + else: + print(regName, "reset val not defined") access = RegElement.get("priv_mode", "") if Registers.get(register, {}).get("description", "") is not None: diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 6f9002c6a..33aeee52d 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -170,7 +170,7 @@ module cva6_mmu // Assignments assign itlb_lu_access = icache_areq_i.fetch_req; - assign dtlb_lu_access = lsu_req_i; + assign dtlb_lu_access = lsu_req_i & !misaligned_ex_i.valid; assign itlb_lu_asid = v_i ? vs_asid_i : asid_i; assign dtlb_lu_asid = (ld_st_v_i || flush_tlb_vvma_i) ? vs_asid_i : asid_i;