diff --git a/Makefile b/Makefile index f987ad84c..570fe74af 100644 --- a/Makefile +++ b/Makefile @@ -42,6 +42,11 @@ BOARD ?= genesys2 mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) root-dir := $(dir $(mkfile_path)) +ifndef CVA6_REPO_DIR +$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you...) +export CVA6_REPO_DIR = $(abspath $(root-dir)) +endif + support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') > /dev/null 2>&1 ; echo $$?) ifeq ($(support_verilator_4), 0) verilator_threads := 1 @@ -85,25 +90,11 @@ target ?= cv64a6_imafdc_sv39 # Sources # Package files -> compile first -ariane_pkg := core/include/$(target)_config_pkg.sv -ariane_pkg += core/include/riscv_pkg.sv \ - corev_apu/riscv-dbg/src/dm_pkg.sv \ - core/include/ariane_pkg.sv \ - core/include/ariane_rvfi_pkg.sv \ - core/include/wt_cache_pkg.sv \ - core/include/cvxif_pkg.sv \ - corev_apu/axi/src/axi_pkg.sv \ +ariane_pkg := \ corev_apu/register_interface/src/reg_intf.sv \ - core/include/axi_intf.sv \ corev_apu/tb/rvfi_pkg.sv \ corev_apu/tb/ariane_soc_pkg.sv \ - corev_apu/tb/ariane_axi_soc_pkg.sv \ - core/include/ariane_axi_pkg.sv \ - core/include/std_cache_pkg.sv \ - core/fpu/src/fpnew_pkg.sv \ - common/submodules/common_cells/src/cf_math_pkg.sv \ - core/cvxif_example/include/cvxif_instr_pkg.sv \ - core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv + corev_apu/tb/ariane_axi_soc_pkg.sv ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg)) # utility modules @@ -156,13 +147,7 @@ endif # this list contains the standalone components -src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) \ - $(filter-out core/fpu/src/fpnew_pkg.sv, $(wildcard core/fpu/src/*.sv)) \ - $(filter-out core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \ - $(wildcard core/fpu/src/fpu_div_sqrt_mvp/hdl/*.sv)) \ - $(wildcard core/frontend/*.sv) \ - $(filter-out core/cache_subsystem/std_no_dcache.sv, \ - $(wildcard core/cache_subsystem/*.sv)) \ +src := core/axi_adapter.sv \ $(wildcard corev_apu/bootrom/*.sv) \ $(wildcard corev_apu/clint/*.sv) \ $(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \ @@ -170,8 +155,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \ $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \ $(wildcard corev_apu/axi_mem_if/src/*.sv) \ - $(wildcard core/pmp/src/*.sv) \ - $(wildcard core/cvxif_example/*.sv) \ corev_apu/rv_plic/rtl/rv_plic_target.sv \ corev_apu/rv_plic/rtl/rv_plic_gateway.sv \ corev_apu/rv_plic/rtl/plic_regmap.sv \ @@ -203,34 +186,17 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) corev_apu/axi/src/axi_mux.sv \ corev_apu/axi/src/axi_demux.sv \ corev_apu/axi/src/axi_xbar.sv \ - common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv \ - common/submodules/common_cells/src/unread.sv \ - common/submodules/common_cells/src/sync.sv \ common/submodules/common_cells/src/cdc_2phase.sv \ common/submodules/common_cells/src/spill_register_flushable.sv \ common/submodules/common_cells/src/spill_register.sv \ - common/submodules/common_cells/src/sync_wedge.sv \ - common/submodules/common_cells/src/edge_detect.sv \ common/submodules/common_cells/src/stream_arbiter.sv \ common/submodules/common_cells/src/stream_arbiter_flushable.sv \ common/submodules/common_cells/src/deprecated/fifo_v1.sv \ common/submodules/common_cells/src/deprecated/fifo_v2.sv \ - common/submodules/common_cells/src/fifo_v3.sv \ - common/submodules/common_cells/src/lzc.sv \ - common/submodules/common_cells/src/popcount.sv \ - common/submodules/common_cells/src/rr_arb_tree.sv \ - common/submodules/common_cells/src/deprecated/rrarbiter.sv \ common/submodules/common_cells/src/stream_delay.sv \ - common/submodules/common_cells/src/lfsr.sv \ - common/submodules/common_cells/src/lfsr_8bit.sv \ common/submodules/common_cells/src/lfsr_16bit.sv \ - common/submodules/common_cells/src/delta_counter.sv \ - common/submodules/common_cells/src/counter.sv \ - common/submodules/common_cells/src/shift_reg.sv \ corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv \ corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv \ - common/local/util/tc_sram_wrapper.sv \ - corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv \ corev_apu/src/tech_cells_generic/src/rtl/tc_clk.sv \ corev_apu/tb/ariane_testharness.sv \ corev_apu/tb/ariane_peripherals.sv \ @@ -255,7 +221,7 @@ copro_src := $(addprefix $(root-dir), $(copro_src)) uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd) uart_src := $(addprefix $(root-dir), $(uart_src)) -fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv +fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv fpga_src := $(addprefix $(root-dir), $(fpga_src)) # look for testbenches @@ -324,12 +290,11 @@ endif vcs_build: $(dpi-library)/ariane_dpi.so mkdir -p $(vcs-library) cd $(vcs-library) &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+$(defines) $(filter %.sv,$(util)) +incdir+../common/local/util+../core/include/+src/util/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -f ../core/Flist.$(target) &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\ vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(filter %.sv,$(copro_src)) &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../core/include/+../common/submodules/common_cells/include/+../common/local/util/+../corev_apu/axi/include/+../corev_apu/register_interface/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../common/submodules/common_cells/include/+../corev_apu/axi/include/+../corev_apu/register_interface/include/ &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\ vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) +incdir+../corev_apu/axi/include/ &&\ vcs $(if $(VERDI), -kdb -debug_access+all -lca,) -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb @@ -344,12 +309,10 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari # src files $(library)/.build-srcs: $(util) $(library) $(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 - # $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg)) - $(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583 # Suppress message that always_latch may not be checked thoroughly by QuestaSim. $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src)) - # $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src)) $(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583 + $(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors -f ../core/Flist.$(target) $(list_incdir) -suppress 2583 touch $(library)/.build-srcs # build TBs @@ -478,9 +441,9 @@ XRUN_COMP = $(XRUN_COMP_FLAGS) \ $(XRUN_DISABLED_WARNINGS) \ $(XRUN_INCDIR) \ $(filter %.sv, $(ariane_pkg)) \ - $(filter %.sv, $(util)) \ $(filter %.vhd, $(uart_src)) \ $(filter %.sv, $(src)) \ + -f ../core/Flist.$(target) \ $(filter %.sv, $(XRUN_TB)) \ XRUN_RUN = $(XRUN_RUN_FLAGS) \ @@ -584,11 +547,10 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma # verilator-specific verilate_command := $(verilator) \ + -f core/Flist.$(target) \ $(filter-out %.vhd, $(ariane_pkg)) \ $(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \ - $(copro_src) \ +define+$(defines)$(if $(TRACE_FAST),+VM_TRACE)$(if $(TRACE_COMPACT),+VM_TRACE+VM_TRACE_FST) \ - common/local/util/sram.sv \ corev_apu/tb/common/mock_uart.sv \ +incdir+corev_apu/axi_node \ $(if $(verilator_threads), --threads $(verilator_threads)) \ @@ -764,6 +726,7 @@ check-torture: grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig +src_flist := $(addprefix $(root-dir), $(shell cat core/Flist.$(target)|grep "$\{CVA6_REPO_DIR.\+sv"|sed "s/.*CVA6_REPO_DIR..//")) fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv) fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv) fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv) @@ -773,12 +736,11 @@ fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv) fpga_filter += $(addprefix $(root-dir), corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv) fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv) -fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) $(copro_src) +fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist) @echo "[FPGA] Generate sources" @echo read_vhdl {$(uart_src)} > corev_apu/fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl - @echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> corev_apu/fpga/scripts/add_sources.tcl - @echo read_verilog -sv {$(filter-out $(fpga_filter), $(copro_src))} >> corev_apu/fpga/scripts/add_sources.tcl + @echo read_verilog -sv {$(filter-out $(fpga_filter), $(src_flist))} >> corev_apu/fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> corev_apu/fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(fpga_src)} >> corev_apu/fpga/scripts/add_sources.tcl @echo "[FPGA] Generate Bitstream"