diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst
index 6adcdb438..3f860d655 100644
--- a/docs/01_cva6_user/Programmer_View.rst
+++ b/docs/01_cva6_user/Programmer_View.rst
@@ -75,6 +75,7 @@ These extensions are available in CV32A60AX:
    "RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)",                       "✔"
    "RV32C - Compressed Instructions ",                                      "✔"
    "RV32Zcb - Code Size Reduction",                                         "✔"
+   "RVZcmp - Code Size Reduction",                                          ""
    "RV32D - Double precision floating-point",                               ""
    "RV32F - Single precision floating-point",                               ""
    "RV32M - Integer Multiply/Divide",                                       "✔"
@@ -98,6 +99,7 @@ These extensions are available in CV32A60X:
    "RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)",                       "✔"
    "RV32C - Compressed Instructions ",                                      "✔"
    "RV32Zcb - Code Size Reduction",                                         "✔"
+   "RVZcmp - Code Size Reduction",                                          "✔"
    "RV32D - Double precision floating-point",                               ""
    "RV32F - Single precision floating-point",                               ""
    "RV32M - Integer Multiply/Divide",                                       "✔"
diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst b/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst
index 8e3d23bda..de4d49883 100644
--- a/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst
+++ b/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst
@@ -25,7 +25,6 @@
    :align: left
    :header: "Configuration", "Implementation"
 
-   "CV32A60AX", "Implemented extension"
    "CV32A60X", "Implemented extension"
 
 **Note**: Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles.  
@@ -35,7 +34,7 @@ RVZcmp Code Size Reduction Instructions
 
 Zcmp belongs to group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of Standard C extension adding more 16-bit instructions to the ISA.
 Zcmp includes 16-bit macro instructions, PUSH/POP and double move, which reuse the encoding for c.fsdsp instruction.
-All the Zcmp instructions require at least standard C extension support as pre-requisite, along with Zca extension.
+All the Zcmp instructions require at least C extension support with Zcd extension disabled as pre-requisite.
 
 - **CM.PUSH**: Compressed Push
 
diff --git a/docs/01_cva6_user/index.rst b/docs/01_cva6_user/index.rst
index 255fa8544..d2635f0cd 100644
--- a/docs/01_cva6_user/index.rst
+++ b/docs/01_cva6_user/index.rst
@@ -37,6 +37,7 @@ CVA6 User Manual
    RV32A <RISCV_Instructions_RV32A>
    RV32C <RISCV_Instructions_RV32C>
    RV32Zcb <RISCV_Instructions_RV32ZCb>
+   RVZcmp <RISCV_Instructions_RVZcmp>
    RVZba <RISCV_Instructions_RVZba>
    RVZbb <RISCV_Instructions_RVZbb>
    RVZbc <RISCV_Instructions_RVZbc>