diff --git a/Makefile b/Makefile
index 61007ccd7..5fba194a9 100755
--- a/Makefile
+++ b/Makefile
@@ -52,9 +52,10 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))      \
         src/fpga-support/rtl/SyncSpRamBeNx64.sv                        \
         src/common_cells/src/deprecated/generic_fifo.sv                \
         src/common_cells/src/deprecated/pulp_sync.sv                   \
-		src/common_cells/src/fifo_v2.sv                                \
+        src/common_cells/src/fifo_v2.sv                                \
         src/common_cells/src/lzc.sv                                    \
         src/common_cells/src/rrarbiter.sv                              \
+        src/common_cells/src/lfsr_8bit.sv                              \
         tb/ariane_testharness.sv                                       \
         tb/common/SimDTM.sv                                            \
         tb/common/SimJTAG.sv                                           
diff --git a/src/cache_subsystem/lfsr.sv b/src/cache_subsystem/lfsr.sv
deleted file mode 100644
index 7a0e76d28..000000000
--- a/src/cache_subsystem/lfsr.sv
+++ /dev/null
@@ -1,68 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//
-// Author: Igor Loi - University of Bologna
-// Author: Florian Zaruba, ETH Zurich
-// Date: 12.11.2017
-// Description: 8-bit LFSR
-
-// --------------
-// 8-bit LFSR
-// --------------
-//
-// Description: Shift register for way selection
-//
-module lfsr #(
-        parameter logic [7:0]  SEED  = 8'b0,
-        parameter int unsigned WIDTH = 8
-    )(
-        input  logic                      clk_i,
-        input  logic                      rst_ni,
-        input  logic                      en_i,
-        output logic [WIDTH-1:0]          refill_way_oh,
-        output logic [$clog2(WIDTH)-1:0]  refill_way_bin
-    );
-
-    localparam int unsigned LOG_WIDTH = $clog2(WIDTH);
-
-    logic [7:0] shift_d, shift_q;
-
-
-    always_comb begin
-
-        automatic logic shift_in;
-        shift_in = !(shift_q[7] ^ shift_q[3] ^ shift_q[2] ^ shift_q[1]);
-
-        shift_d = shift_q;
-
-        if (en_i)
-            shift_d = {shift_q[6:0], shift_in};
-
-        // output assignment
-        refill_way_oh = 'b0;
-        refill_way_oh[shift_q[LOG_WIDTH-1:0]] = 1'b1;
-        refill_way_bin = shift_q[$clog2(WIDTH)-1:0];
-    end
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin : proc_
-        if(~rst_ni) begin
-            shift_q <= SEED;
-        end else begin
-            shift_q <= shift_d;
-        end
-    end
-
-    `ifndef SYNTHESIS
-        initial begin
-            assert (WIDTH <= 8) else $fatal(1, "WIDTH needs to be less than 8 because of the 8-bit LFSR");
-        end
-    `endif
-
-endmodule
diff --git a/src/cache_subsystem/miss_handler.sv b/src/cache_subsystem/miss_handler.sv
index f4c3b1ff4..d09e8ff90 100644
--- a/src/cache_subsystem/miss_handler.sv
+++ b/src/cache_subsystem/miss_handler.sv
@@ -474,7 +474,7 @@ module miss_handler #(
     // -----------------
     // Replacement LFSR
     // -----------------
-    lfsr #(.WIDTH (DCACHE_SET_ASSOC)) i_lfsr (
+    lfsr_8bit #(.WIDTH (DCACHE_SET_ASSOC)) i_lfsr (
         .en_i           ( lfsr_enable ),
         .refill_way_oh  ( lfsr_oh     ),
         .refill_way_bin ( lfsr_bin    ),
diff --git a/src/cache_subsystem/std_icache.sv b/src/cache_subsystem/std_icache.sv
index 577fb001a..7818c1d97 100644
--- a/src/cache_subsystem/std_icache.sv
+++ b/src/cache_subsystem/std_icache.sv
@@ -413,7 +413,7 @@ module std_icache  #(
     // -----------------
     // Replacement LFSR
     // -----------------
-    lfsr #(.WIDTH (ICACHE_SET_ASSOC)) i_lfsr (
+    lfsr_8bit #(.WIDTH (ICACHE_SET_ASSOC)) i_lfsr (
         .clk_i          ( clk_i       ),
         .rst_ni         ( rst_ni      ),
         .en_i           ( update_lfsr ),