diff --git a/include/mem_if.svh b/include/mem_if.svh
index 9e6896381..e0f70dff6 100644
--- a/include/mem_if.svh
+++ b/include/mem_if.svh
@@ -35,6 +35,7 @@ interface mem_if
 
         // Memory interface configured as master
         // we are also synthesizing this interface
+        `ifndef VERILATOR
         `ifndef SYNTHESIS
         clocking mck @(posedge clk);
             default input #1ns output #1ns;
@@ -54,18 +55,24 @@ interface mem_if
                    data_gnt, data_rvalid, data_rdata;
         endclocking
         `endif
+        `endif
+
 
         modport master (
+            `ifndef VERILATOR
             `ifndef SYNTHESIS
             clocking mck,
             `endif
+            `endif
             input   address, data_wdata, data_req, data_we, data_be,
             output  data_gnt, data_rvalid, data_rdata
         );
         modport slave  (
+            `ifndef VERILATOR
             `ifndef SYNTHESIS
             clocking sck,
             `endif
+            `endif
             output  address, data_wdata, data_req, data_we, data_be,
             input   data_gnt, data_rvalid, data_rdata
         );
diff --git a/src/lsu.sv b/src/lsu.sv
index 3e038dd2a..c94727152 100644
--- a/src/lsu.sv
+++ b/src/lsu.sv
@@ -103,7 +103,6 @@ module lsu #(
     // Address Generation Unit (AGU)
     // ------------------------------
     assign vaddr_i = imm_i + operand_a_i;
-    assign data_if.address = vaddr_i;
 
     // ---------------
     // Memory Arbiter
@@ -155,7 +154,7 @@ module lsu #(
     assign address_i [1]       = paddr_o;
     // this is a read only interface
     assign data_we_i    [1]    = 1'b0;
-    assign data_wdata_i [1]    = 1'b0;
+    assign data_wdata_i [1]    = 64'b0;
     assign data_be_i    [1]    = be;
     logic [63:0] rdata;
     // data coming from arbiter interface 1
@@ -422,22 +421,12 @@ module lsu #(
     // Byte Enable - TODO: Find a more beautiful way to accomplish this functionality
     // ---------------
     always_comb begin : byte_enable
-        be = 8'b0;
         // we can generate the byte enable from the virtual address since the last
         // 12 bit are the same anyway
         // and we can always generate the byte enable from the address at hand
         case (operator)
             LD, SD: // double word
-                case (vaddr[2:0])
-                    3'b000: be = 8'b1111_1111;
-                    // 3'b001: be = 8'b1111_1110;
-                    // 3'b010: be = 8'b1111_1100;
-                    // 3'b011: be = 8'b1111_1000;
-                    // 3'b100: be = 8'b1111_0000;
-                    // 3'b101: be = 8'b1110_0000;
-                    // 3'b110: be = 8'b1100_0000;
-                    // 3'b111: be = 8'b1000_0000;
-                endcase
+                    be = 8'b1111_1111;
             LW, LWU, SW: // word
                 case (vaddr[2:0])
                     3'b000: be = 8'b0000_1111;
@@ -445,9 +434,7 @@ module lsu #(
                     3'b010: be = 8'b0011_1100;
                     3'b011: be = 8'b0111_1000;
                     3'b100: be = 8'b1111_0000;
-                    // 3'b101: be = 8'b1110_0000;
-                    // 3'b110: be = 8'b1100_0000;
-                    // 3'b111: be = 8'b1000_0000;
+                    default:;
                 endcase
             LH, LHU, SH: // half word
                 case (vaddr[2:0])
@@ -458,7 +445,7 @@ module lsu #(
                     3'b100: be = 8'b0011_0000;
                     3'b101: be = 8'b0110_0000;
                     3'b110: be = 8'b1100_0000;
-                    // 3'b111: be = 8'b1000_0000;
+                    default:;
                 endcase
             LB, LBU, SB: // byte
                 case (vaddr[2:0])
@@ -471,6 +458,8 @@ module lsu #(
                     3'b110: be = 8'b0100_0000;
                     3'b111: be = 8'b1000_0000;
                 endcase
+            default:
+                be = 8'b0;
         endcase
     end
 
diff --git a/src/mem_arbiter.sv b/src/mem_arbiter.sv
index 6c5a13d7c..5b0725974 100644
--- a/src/mem_arbiter.sv
+++ b/src/mem_arbiter.sv
@@ -103,7 +103,7 @@ module mem_arbiter #(
                     if (data_gnt_i) begin
                         data_gnt_o[i] = data_gnt_i;
                         // set the slave on which we are waiting
-                        data_i = i;
+                        data_i = i[NR_PORTS-1:0];
                         push_i = 1'b1;
                     end
                     break; // break here as this is a priority select
@@ -125,8 +125,12 @@ module mem_arbiter #(
         if (data_rvalid_i) begin
             // pass the read to the appropriate slave
             pop_i                 = 1'b1;
-            data_rvalid_o[data_o] = data_rvalid_i;
-            data_rdata_o[data_o]  = data_rdata_i;
+            for (int i = 0; i < NR_PORTS; i++) begin
+                if (data_o[i] == 1'b1) begin
+                    data_rvalid_o[i] = data_rvalid_i;
+                    data_rdata_o[i]  = data_rdata_i;
+                end
+            end
         end
     end
 
diff --git a/src/mmu.sv b/src/mmu.sv
index 4dfc27e92..3879214ec 100644
--- a/src/mmu.sv
+++ b/src/mmu.sv
@@ -206,8 +206,9 @@ module mmu #(
         // an error.
         if (enable_translation_i) begin
             fetch_req = 1'b0;
+            /* verilator lint_off WIDTH */
             fetch_paddr = {itlb_content.ppn, fetch_vaddr_i[11:0]};
-
+            /* verilator lint_on WIDTH */
             if (itlb_is_2M) begin
               fetch_paddr[20:12] = fetch_vaddr_i[20:12];
             end
diff --git a/src/ptw.sv b/src/ptw.sv
index cfda4a069..9ee9914b7 100644
--- a/src/ptw.sv
+++ b/src/ptw.sv
@@ -17,7 +17,7 @@
 // (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
 // University of Bologna.
 //
-
+/* verilator lint_off WIDTH */
 import ariane_pkg::*;
 
 module ptw #(
@@ -266,4 +266,5 @@ module ptw #(
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule
+/* verilator lint_on WIDTH */
\ No newline at end of file