From bc41a0b7fbd30639b7e5df2fa81e9d7ba307afe5 Mon Sep 17 00:00:00 2001 From: Yannick Casamatta Date: Thu, 7 Mar 2024 18:34:27 +0100 Subject: [PATCH] Modify rvfi probes for param change (#1900) --- core/cva6_rvfi.sv | 67 +++++++++++++++++++---------- core/cva6_rvfi_probes.sv | 22 ++++++++-- core/include/ariane_pkg.sv | 20 ++++++--- corev_apu/fpga/src/ariane_xilinx.sv | 2 - corev_apu/tb/ariane_tb.sv | 2 - corev_apu/tb/ariane_testharness.sv | 1 - 6 files changed, 76 insertions(+), 38 deletions(-) diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index 5fcd0c10e..bfdc26c33 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -68,11 +68,24 @@ module cva6_rvfi riscv::xlen_t rs1_forwarding; riscv::xlen_t rs2_forwarding; - scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr; - exception_t ex_commit; + logic [CVA6Cfg.NrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_pc; + fu_op [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_instr_op; + logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1; + logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2; + logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd; + riscv::xlen_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_result; + logic [CVA6Cfg.NrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_valid; + + riscv::xlen_t ex_commit_cause; + logic ex_commit_valid; + riscv::priv_lvl_t priv_lvl; - lsu_ctrl_t lsu_ctrl; + logic [riscv::VLEN-1:0] lsu_ctrl_vaddr; + fu_t lsu_ctrl_fu; + logic [(riscv::XLEN/8)-1:0] lsu_ctrl_be; + logic [TRANS_ID_BITS-1:0] lsu_ctrl_trans_id; + logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; logic [riscv::PLEN-1:0] mem_paddr; @@ -120,21 +133,29 @@ module cva6_rvfi assign rs1_forwarding = instr.rs1_forwarding; assign rs2_forwarding = instr.rs2_forwarding; - assign commit_instr = instr.commit_instr; - assign ex_commit = instr.ex_commit; + assign commit_instr_pc = instr.commit_instr_pc; + assign commit_instr_op = instr.commit_instr_op; + assign commit_instr_rs1 = instr.commit_instr_rs1; + assign commit_instr_rs2 = instr.commit_instr_rs2; + assign commit_instr_rd = instr.commit_instr_rd; + assign commit_instr_result = instr.commit_instr_result; + assign commit_instr_valid = instr.commit_instr_valid; + + assign ex_commit_cause = instr.ex_commit_cause; + assign ex_commit_valid = instr.ex_commit_valid; + assign priv_lvl = instr.priv_lvl; - assign lsu_ctrl = instr.lsu_ctrl; assign wbdata = instr.wbdata; assign commit_ack = instr.commit_ack; assign mem_paddr = instr.mem_paddr; assign debug_mode = instr.debug_mode; assign wdata = instr.wdata; - assign lsu_addr = lsu_ctrl.vaddr; - assign lsu_rmask = lsu_ctrl.fu == LOAD ? lsu_ctrl.be : '0; - assign lsu_wmask = lsu_ctrl.fu == STORE ? lsu_ctrl.be : '0; - assign lsu_addr_trans_id = lsu_ctrl.trans_id; + assign lsu_addr = instr.lsu_ctrl_vaddr; + assign lsu_rmask = instr.lsu_ctrl_fu == LOAD ? instr.lsu_ctrl_be : '0; + assign lsu_wmask = instr.lsu_ctrl_fu == STORE ? instr.lsu_ctrl_be : '0; + assign lsu_addr_trans_id = instr.lsu_ctrl_trans_id; //ID STAGE @@ -220,30 +241,30 @@ module cva6_rvfi always_comb begin for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin logic exception; - exception = commit_instr[i].valid && ex_commit.valid; - rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit.valid) || - (exception && (ex_commit.cause == riscv::ENV_CALL_MMODE || - ex_commit.cause == riscv::ENV_CALL_SMODE || - ex_commit.cause == riscv::ENV_CALL_UMODE)); + exception = commit_instr_valid[i] && ex_commit_valid; + rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit_valid) || + (exception && (ex_commit_cause == riscv::ENV_CALL_MMODE || + ex_commit_cause == riscv::ENV_CALL_SMODE || + ex_commit_cause == riscv::ENV_CALL_UMODE)); rvfi_instr_o[i].insn = mem_q[commit_pointer[i]].instr; // when trap, the instruction is not executed rvfi_instr_o[i].trap = exception; - rvfi_instr_o[i].cause = ex_commit.cause; + rvfi_instr_o[i].cause = ex_commit_cause; rvfi_instr_o[i].mode = (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; rvfi_instr_o[i].ixl = riscv::XLEN == 64 ? 2 : 1; - rvfi_instr_o[i].rs1_addr = commit_instr[i].rs1[4:0]; - rvfi_instr_o[i].rs2_addr = commit_instr[i].rs2[4:0]; - rvfi_instr_o[i].rd_addr = commit_instr[i].rd[4:0]; - rvfi_instr_o[i].rd_wdata = (FpPresent && is_rd_fpr(commit_instr[i].op)) ? - commit_instr[i].result : wdata[i]; - rvfi_instr_o[i].pc_rdata = commit_instr[i].pc; + rvfi_instr_o[i].rs1_addr = commit_instr_rs1[i][4:0]; + rvfi_instr_o[i].rs2_addr = commit_instr_rs2[i][4:0]; + rvfi_instr_o[i].rd_addr = commit_instr_rd[i][4:0]; + rvfi_instr_o[i].rd_wdata = (FpPresent && is_rd_fpr(commit_instr_op[i])) ? + commit_instr_result[i] : wdata[i]; + rvfi_instr_o[i].pc_rdata = commit_instr_pc[i]; rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr; // So far, only write paddr is reported. TODO: read paddr rvfi_instr_o[i].mem_paddr = mem_paddr; rvfi_instr_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask; rvfi_instr_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata; rvfi_instr_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask; - rvfi_instr_o[i].mem_rdata = commit_instr[i].result; + rvfi_instr_o[i].mem_rdata = commit_instr_result[i]; rvfi_instr_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata; rvfi_instr_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata; end diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index ef717d1f4..db7d9e455 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -72,16 +72,32 @@ module cva6_rvfi_probes instr.rs1_forwarding = rs1_forwarding_i; instr.rs2_forwarding = rs2_forwarding_i; - instr.ex_commit = ex_commit_i; + instr.ex_commit_cause = ex_commit_i.cause; + instr.ex_commit_valid = ex_commit_i.valid; + instr.priv_lvl = priv_lvl_i; - instr.lsu_ctrl = lsu_ctrl_i; + instr.lsu_ctrl_vaddr = lsu_ctrl_i.vaddr; + instr.lsu_ctrl_fu = lsu_ctrl_i.fu; + instr.lsu_ctrl_be = lsu_ctrl_i.be; + instr.lsu_ctrl_trans_id = lsu_ctrl_i.trans_id; + instr.wbdata = wbdata_i; instr.mem_paddr = mem_paddr_i; instr.debug_mode = debug_mode_i; instr.commit_pointer = commit_pointer_i; - instr.commit_instr = commit_instr_i; + + for (int i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin + instr.commit_instr_pc[i] = commit_instr_i[i].pc; + instr.commit_instr_op[i] = commit_instr_i[i].op; + instr.commit_instr_rs1[i] = commit_instr_i[i].rs1; + instr.commit_instr_rs2[i] = commit_instr_i[i].rs2; + instr.commit_instr_rd[i] = commit_instr_i[i].rd; + instr.commit_instr_result[i] = commit_instr_i[i].result; + instr.commit_instr_valid[i] = commit_instr_i[i].valid; + end + instr.commit_ack = commit_ack_i; instr.wdata = wdata_i; diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index c5281670d..cd242c5fb 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -846,10 +846,20 @@ package ariane_pkg; logic is_compressed; riscv::xlen_t rs1_forwarding; riscv::xlen_t rs2_forwarding; - scoreboard_entry_t [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr; - exception_t ex_commit; + logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_pc; + fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_instr_op; + logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1; + logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2; + logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd; + riscv::xlen_t [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_result; + logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_valid; + riscv::xlen_t ex_commit_cause; + logic ex_commit_valid; riscv::priv_lvl_t priv_lvl; - lsu_ctrl_t lsu_ctrl; + logic [riscv::VLEN-1:0] lsu_ctrl_vaddr; + fu_t lsu_ctrl_fu; + logic [(riscv::XLEN/8)-1:0] lsu_ctrl_be; + logic [TRANS_ID_BITS-1:0] lsu_ctrl_trans_id; logic [((cva6_config_pkg::CVA6ConfigCvxifEn || cva6_config_pkg::CVA6ConfigVExtEn) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_ack; logic [riscv::PLEN-1:0] mem_paddr; @@ -956,14 +966,10 @@ package ariane_pkg; rvfi_csr_elmt_t pmpcfg2; rvfi_csr_elmt_t pmpcfg3; rvfi_csr_elmt_t [15:0] pmpaddr; - } rvfi_csr_t; - localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace; - - // ---------------------- // Arithmetic Functions // ---------------------- diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index 3e44b8af3..70aed05ec 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -154,8 +154,6 @@ module ariane_xilinx ( output logic tx ); -// CVA6 config -localparam bit IsRVFI = bit'(0); // CVA6 Xilinx configuration localparam config_pkg::cva6_user_cfg_t CVA6UserCfg = '{ NrCommitPorts: cva6_config_pkg::CVA6ConfigNrCommitPorts, diff --git a/corev_apu/tb/ariane_tb.sv b/corev_apu/tb/ariane_tb.sv index df05263aa..5c2251869 100644 --- a/corev_apu/tb/ariane_tb.sv +++ b/corev_apu/tb/ariane_tb.sv @@ -30,7 +30,6 @@ module ariane_tb; // cva6 configuration localparam config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); - localparam bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace); static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); @@ -52,7 +51,6 @@ module ariane_tb; ariane_testharness #( .CVA6Cfg ( CVA6Cfg ), - .IsRVFI ( IsRVFI ), // .NUM_WORDS ( NUM_WORDS ), .InclSimDTM ( 1'b1 ), diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index 01c65fe32..933a4e4ea 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -17,7 +17,6 @@ module ariane_testharness #( parameter config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg), - parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace), // parameter int unsigned AXI_USER_WIDTH = ariane_pkg::AXI_USER_WIDTH, parameter int unsigned AXI_USER_EN = ariane_pkg::AXI_USER_EN,