diff --git a/Flist.ariane b/Flist.ariane index 45e1d49b3..52d3f4c35 100644 --- a/Flist.ariane +++ b/Flist.ariane @@ -17,6 +17,9 @@ // Description: File list for OpenPiton flow +incdir+src/common_cells/include/common_cells/ +incdir+src/util/ +src/common_cells/src/deprecated/rrarbiter.sv +src/common_cells/src/deprecated/fifo_v1.sv +src/common_cells/src/deprecated/fifo_v2.sv src/common_cells/src/fifo_v3.sv src/common_cells/src/lfsr_8bit.sv src/common_cells/src/lzc.sv @@ -26,6 +29,8 @@ src/common_cells/src/sync.sv src/common_cells/src/sync_wedge.sv src/common_cells/src/cdc_2phase.sv src/common_cells/src/shift_reg.sv +src/common_cells/src/unread.sv +src/common_cells/src/popcount.sv src/register_interface/src/apb_to_reg.sv src/register_interface/src/reg_intf_pkg.sv src/register_interface/src/reg_intf.sv @@ -64,8 +69,9 @@ include/ariane_axi_pkg.sv include/wt_cache_pkg.sv //include/std_cache_pkg.sv include/axi_intf.sv -src/util/instruction_tracer_if.sv -src/util/instruction_tracer.sv +include/instr_tracer_pkg.sv +src/util/instr_tracer_if.sv +src/util/instr_tracer.sv src/util/sram.sv src/util/axi_master_connect.sv src/util/axi_master_connect_rev.sv @@ -87,13 +93,14 @@ src/csr_buffer.sv src/csr_regfile.sv src/decoder.sv src/ex_stage.sv +src/instr_realign.sv src/frontend/btb.sv src/frontend/bht.sv src/frontend/ras.sv src/frontend/instr_scan.sv +src/frontend/instr_queue.sv src/frontend/frontend.sv src/id_stage.sv -src/instr_realigner.sv src/issue_read_operands.sv src/issue_stage.sv src/load_unit.sv diff --git a/Makefile b/Makefile index ad8459218..a47d05647 100644 --- a/Makefile +++ b/Makefile @@ -67,9 +67,9 @@ ariane_pkg := include/riscv_pkg.sv \ ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg)) # utility modules -util := $(wildcard src/util/*.svh) \ - src/util/instruction_tracer_if.sv \ - src/util/instruction_tracer.sv \ +util := include/instr_tracer_pkg.sv \ + src/util/instr_tracer_if.sv \ + src/util/instr_tracer.sv \ src/tech_cells_generic/src/cluster_clock_gating.sv \ tb/common/mock_uart.sv \ src/util/sram.sv @@ -457,7 +457,11 @@ check-torture: diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv) -fpga_filter += $(addprefix $(root-dir), src/util/instruction_tracer.sv) +fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv) +fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv) +fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv) +fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv) +fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv) fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) @echo "[FPGA] Generate sources" diff --git a/include/instr_tracer_pkg.sv b/include/instr_tracer_pkg.sv new file mode 100644 index 000000000..fee879141 --- /dev/null +++ b/include/instr_tracer_pkg.sv @@ -0,0 +1,200 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 16.05.2017 +// Description: Instruction Tracer Defines + +package instr_tracer_pkg; + + parameter INSTR_NOP = 32'h00_00_00_13; + + parameter INSTR_LUI = { 25'b?, riscv::OpcodeLui }; + parameter INSTR_AUIPC = { 25'b?, riscv::OpcodeAuipc }; + parameter INSTR_JAL = { 25'b?, riscv::OpcodeJal }; + parameter INSTR_JALR = { 17'b?, 3'b000, 5'b?, riscv::OpcodeJalr }; + // BRANCH + parameter INSTR_BEQZ = { 7'b?, 5'b0, 5'b?, 3'b000, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BEQ = { 7'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BNEZ = { 7'b?, 5'b0, 5'b?, 3'b001, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BNE = { 7'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BLTZ = { 7'b?, 5'b0, 5'b?, 3'b100, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BLT = { 7'b?, 5'b?, 5'b?, 3'b100, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BGEZ = { 7'b?, 5'b0, 5'b?, 3'b101, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BGE = { 7'b?, 5'b?, 5'b?, 3'b101, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BLTU = { 7'b?, 5'b?, 5'b?, 3'b110, 5'b?, riscv::OpcodeBranch }; + parameter INSTR_BGEU = { 7'b?, 5'b?, 5'b?, 3'b111, 5'b?, riscv::OpcodeBranch }; + + // OP-IMM + parameter INSTR_LI = { 12'b?, 5'b0, 3'b000, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_ADDI = { 17'b?, 3'b000, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_SLTI = { 17'b?, 3'b010, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_XORI = { 17'b?, 3'b100, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_ORI = { 17'b?, 3'b110, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_ANDI = { 17'b?, 3'b111, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_SLLI = { 6'b000000, 11'b?, 3'b001, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_SRLI = { 6'b000000, 11'b?, 3'b101, 5'b?, riscv::OpcodeOpImm }; + parameter INSTR_SRAI = { 6'b010000, 11'b?, 3'b101, 5'b?, riscv::OpcodeOpImm }; + + // OP-IMM-32 + parameter INSTR_ADDIW = { 17'b?, 3'b000, 5'b?, riscv::OpcodeOpImm32 }; + parameter INSTR_SLLIW = { 7'b0000000, 10'b?, 3'b001, 5'b?, riscv::OpcodeOpImm32 }; + parameter INSTR_SRLIW = { 7'b0000000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOpImm32 }; + parameter INSTR_SRAIW = { 7'b0100000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOpImm32 }; + + // OP + parameter INSTR_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp }; + parameter INSTR_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp }; + parameter INSTR_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, riscv::OpcodeOp }; + parameter INSTR_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, riscv::OpcodeOp }; + parameter INSTR_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, riscv::OpcodeOp }; + parameter INSTR_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, riscv::OpcodeOp }; + parameter INSTR_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp }; + parameter INSTR_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp }; + parameter INSTR_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, riscv::OpcodeOp }; + parameter INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, riscv::OpcodeOp }; + parameter INSTR_MUL = { 7'b0000001, 10'b?, 3'b???, 5'b?, riscv::OpcodeOp }; + + // OP32 + parameter INSTR_ADDW = { 7'b0000000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp32 }; + parameter INSTR_SUBW = { 7'b0100000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp32 }; + parameter INSTR_SLLW = { 7'b0000000, 10'b?, 3'b001, 5'b?, riscv::OpcodeOp32 }; + parameter INSTR_SRLW = { 7'b0000000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp32 }; + parameter INSTR_SRAW = { 7'b0100000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp32 }; + parameter INSTR_MULW = { 7'b0000001, 10'b?, 3'b???, 5'b?, riscv::OpcodeOp32 }; + + // MISC-MEM + parameter INSTR_FENCE = { 4'b0, 8'b?, 13'b0, riscv::OpcodeMiscMem }; + parameter INSTR_FENCEI = { 17'b0, 3'b001, 5'b0, riscv::OpcodeMiscMem }; + + // SYSTEM + parameter INSTR_CSRW = { 12'b?, 5'b?, 3'b001, 5'b0, riscv::OpcodeSystem }; + parameter INSTR_CSRRW = { 12'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeSystem }; + parameter INSTR_CSRR = { 12'b?, 5'b0, 3'b010, 5'b?, riscv::OpcodeSystem }; + parameter INSTR_CSRRS = { 12'b?, 5'b?, 3'b010, 5'b?, riscv::OpcodeSystem }; + parameter INSTR_CSRS = { 12'b?, 5'b?, 3'b010, 5'b0, riscv::OpcodeSystem }; + parameter INSTR_CSRRC = { 12'b?, 5'b?, 3'b011, 5'b?, riscv::OpcodeSystem }; + parameter INSTR_CSRC = { 12'b?, 5'b?, 3'b011, 5'b0, riscv::OpcodeSystem }; + + parameter INSTR_CSRWI = { 17'b?, 3'b101, 5'b0, riscv::OpcodeSystem }; + parameter INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, riscv::OpcodeSystem }; + parameter INSTR_CSRSI = { 17'b?, 3'b110, 5'b0, riscv::OpcodeSystem }; + parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, riscv::OpcodeSystem }; + parameter INSTR_CSRCI = { 17'b?, 3'b111, 5'b0, riscv::OpcodeSystem }; + parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, riscv::OpcodeSystem }; + + parameter INSTR_ECALL = { 12'b000000000000, 13'b0, riscv::OpcodeSystem }; + parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, riscv::OpcodeSystem }; + parameter INSTR_MRET = { 12'b001100000010, 13'b0, riscv::OpcodeSystem }; + parameter INSTR_SRET = { 12'b000100000010, 13'b0, riscv::OpcodeSystem }; + parameter INSTR_DRET = { 12'b011110110010, 13'b0, riscv::OpcodeSystem }; + parameter INSTR_WFI = { 12'b000100000101, 13'b0, riscv::OpcodeSystem }; + parameter INSTR_SFENCE = { 12'b0001001?????, 13'b?, riscv::OpcodeSystem }; + + // RV32M + parameter INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp }; + parameter INSTR_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, riscv::OpcodeOp }; + parameter INSTR_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp }; + parameter INSTR_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, riscv::OpcodeOp }; + parameter INSTR_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, riscv::OpcodeOp }; + + // RVFD + parameter INSTR_FMADD = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeMadd}; + parameter INSTR_FMSUB = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeMsub}; + parameter INSTR_FNSMSUB = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeNmsub}; + parameter INSTR_FNMADD = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeNmadd}; + + parameter INSTR_FADD = { 5'b00000, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FSUB = { 5'b00001, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FMUL = { 5'b00010, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FDIV = { 5'b00011, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FSQRT = { 5'b01011, 2'b?, 5'b0, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FSGNJ = { 5'b00100, 2'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FSGNJN = { 5'b00100, 2'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FSGNJX = { 5'b00100, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FMIN = { 5'b00101, 2'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FMAX = { 5'b00101, 2'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FLE = { 5'b10100, 2'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FLT = { 5'b10100, 2'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FEQ = { 5'b10100, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, riscv::OpcodeOpFp}; + + parameter INSTR_FCVT_F2F = { 5'b01000, 2'b?, 5'b000??, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FMV_F2X = { 5'b11100, 2'b?, 5'b0, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FCLASS = { 5'b11100, 2'b?, 5'b0, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FMV_X2F = { 5'b11110, 2'b?, 5'b0, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FCVT_F2I = { 5'b11000, 2'b?, 5'b000??, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + parameter INSTR_FCVT_I2F = { 5'b11010, 2'b?, 5'b000??, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; + + // A + parameter INSTR_AMO = {25'b?, riscv::OpcodeAmo }; + + // Load/Stores + parameter [31:0] LB = 32'b?????????????????000?????0000011; + parameter [31:0] LH = 32'b?????????????????001?????0000011; + parameter [31:0] LW = 32'b?????????????????010?????0000011; + parameter [31:0] LD = 32'b?????????????????011?????0000011; + parameter [31:0] LBU = 32'b?????????????????100?????0000011; + parameter [31:0] LHU = 32'b?????????????????101?????0000011; + parameter [31:0] LWU = 32'b?????????????????110?????0000011; + parameter [31:0] FLW = 32'b?????????????????010?????0000111; + parameter [31:0] FLD = 32'b?????????????????011?????0000111; + parameter [31:0] FLQ = 32'b?????????????????100?????0000111; + parameter [31:0] SB = 32'b?????????????????000?????0100011; + parameter [31:0] SH = 32'b?????????????????001?????0100011; + parameter [31:0] SW = 32'b?????????????????010?????0100011; + parameter [31:0] SD = 32'b?????????????????011?????0100011; + parameter [31:0] FSW = 32'b?????????????????010?????0100111; + parameter [31:0] FSD = 32'b?????????????????011?????0100111; + parameter [31:0] FSQ = 32'b?????????????????100?????0100111; + parameter [31:0] C_ADDI4SPN = 32'b????????????????000???????????00; + parameter [31:0] C_FLD = 32'b????????????????001???????????00; + parameter [31:0] C_LW = 32'b????????????????010???????????00; + parameter [31:0] C_FLW = 32'b????????????????011???????????00; + parameter [31:0] C_FSD = 32'b????????????????101???????????00; + parameter [31:0] C_SW = 32'b????????????????110???????????00; + parameter [31:0] C_FSW = 32'b????????????????111???????????00; + parameter [31:0] C_ADDI = 32'b????????????????000???????????01; + parameter [31:0] C_JAL = 32'b????????????????001???????????01; + parameter [31:0] C_LI = 32'b????????????????010???????????01; + parameter [31:0] C_LUI = 32'b????????????????011???????????01; + parameter [31:0] C_SRLI = 32'b????????????????100?00????????01; + parameter [31:0] C_SRAI = 32'b????????????????100?01????????01; + parameter [31:0] C_ANDI = 32'b????????????????100?10????????01; + parameter [31:0] C_SUB = 32'b????????????????100011???00???01; + parameter [31:0] C_XOR = 32'b????????????????100011???01???01; + parameter [31:0] C_OR = 32'b????????????????100011???10???01; + parameter [31:0] C_AND = 32'b????????????????100011???11???01; + parameter [31:0] C_SUBW = 32'b????????????????100111???00???01; + parameter [31:0] C_ADDW = 32'b????????????????100111???01???01; + parameter [31:0] C_J = 32'b????????????????101???????????01; + parameter [31:0] C_BEQZ = 32'b????????????????110???????????01; + parameter [31:0] C_BNEZ = 32'b????????????????111???????????01; + parameter [31:0] C_SLLI = 32'b????????????????000???????????10; + parameter [31:0] C_FLDSP = 32'b????????????????001???????????10; + parameter [31:0] C_LWSP = 32'b????????????????010???????????10; + parameter [31:0] C_FLWSP = 32'b????????????????011???????????10; + parameter [31:0] C_MV = 32'b????????????????1000??????????10; + parameter [31:0] C_ADD = 32'b????????????????1001??????????10; + parameter [31:0] C_FSDSP = 32'b????????????????101???????????10; + parameter [31:0] C_SWSP = 32'b????????????????110???????????10; + parameter [31:0] C_FSWSP = 32'b????????????????111???????????10; + parameter [31:0] C_NOP = 32'b????????????????0000000000000001; + parameter [31:0] C_ADDI16SP = 32'b????????????????011?00010?????01; + parameter [31:0] C_JR = 32'b????????????????1000?????0000010; + parameter [31:0] C_JALR = 32'b????????????????1001?????0000010; + parameter [31:0] C_EBREAK = 32'b????????????????1001000000000010; + parameter [31:0] C_LD = 32'b????????????????011???????????00; + parameter [31:0] C_SD = 32'b????????????????111???????????00; + parameter [31:0] C_ADDIW = 32'b????????????????001???????????01; + parameter [31:0] C_LDSP = 32'b????????????????011???????????10; + parameter [31:0] C_SDSP = 32'b????????????????111???????????10; + +endpackage \ No newline at end of file diff --git a/openpiton/ariane_verilog_wrap.sv b/openpiton/ariane_verilog_wrap.sv index babda5c12..2f6044265 100644 --- a/openpiton/ariane_verilog_wrap.sv +++ b/openpiton/ariane_verilog_wrap.sv @@ -14,21 +14,24 @@ module ariane_verilog_wrap #( + parameter int unsigned RASDepth = 2, + parameter int unsigned BTBEntries = 32, + parameter int unsigned BHTEntries = 128, // debug module base address parameter logic [63:0] DmBaseAddress = 64'h0, // swap endianess in l15 adapter parameter bit SwapEndianess = 1, // PMA configuration // idempotent region - parameter int NrNonIdempotentRules = 0, + parameter int unsigned NrNonIdempotentRules = 0, parameter logic [NrMaxRules*64-1:0] NonIdempotentAddrBase = '0, parameter logic [NrMaxRules*64-1:0] NonIdempotentLength = '0, // executable regions - parameter int NrExecuteRegionRules = 0, + parameter int unsigned NrExecuteRegionRules = 0, parameter logic [NrMaxRules*64-1:0] ExecuteRegionAddrBase = '0, parameter logic [NrMaxRules*64-1:0] ExecuteRegionLength = '0, // cacheable regions - parameter int NrCachedRegionRules = 0, + parameter int unsigned NrCachedRegionRules = 0, parameter logic [NrMaxRules*64-1:0] CachedRegionAddrBase = '0, parameter logic [NrMaxRules*64-1:0] CachedRegionLength = '0 ) ( @@ -164,6 +167,9 @@ module ariane_verilog_wrap #( ///////////////////////////// localparam ariane_pkg::ariane_cfg_t ArianeOpenPitonCfg = '{ + RASDepth: RASDepth, + BTBEntries: BTBEntries, + BHTEntries: BHTEntries, // idempotent region NrNonIdempotentRules: NrNonIdempotentRules, NonIdempotentAddrBase: NonIdempotentAddrBase, diff --git a/src/ariane.sv b/src/ariane.sv index edd23033a..a6d2ce3b5 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -704,7 +704,7 @@ module ariane #( `endif // PITON_ARIANE `ifndef VERILATOR - instruction_tracer_if tracer_if (clk_i); + instr_tracer_if tracer_if (clk_i); // assign instruction tracer interface // control signals assign tracer_if.rstn = rst_ni; @@ -741,7 +741,7 @@ module ariane #( assign tracer_if.priv_lvl = priv_lvl; assign tracer_if.debug_mode = debug_mode; - instruction_tracer instr_tracer_i ( + instr_tracer instr_tracer_i ( .tracer_if(tracer_if), .hart_id_i ); diff --git a/src/decoder.sv b/src/decoder.sv index 9637c0f71..e22067447 100644 --- a/src/decoder.sv +++ b/src/decoder.sv @@ -73,7 +73,7 @@ module decoder ( instruction_o.pc = pc_i; instruction_o.trans_id = 5'b0; instruction_o.fu = NONE; - instruction_o.op = ADD; + instruction_o.op = ariane_pkg::ADD; instruction_o.rs1 = '0; instruction_o.rs2 = '0; instruction_o.rd = '0; @@ -106,24 +106,24 @@ module decoder ( 12'b1: ebreak = 1'b1; // SRET 12'b1_0000_0010: begin - instruction_o.op = SRET; + instruction_o.op = ariane_pkg::SRET; // check privilege level, SRET can only be executed in S and M mode // we'll just decode an illegal instruction if we are in the wrong privilege level if (priv_lvl_i == riscv::PRIV_LVL_U) begin illegal_instr = 1'b1; // do not change privilege level if this is an illegal instruction - instruction_o.op = ADD; + instruction_o.op = ariane_pkg::ADD; end // if we are in S-Mode and Trap SRET (tsr) is set -> trap on illegal instruction if (priv_lvl_i == riscv::PRIV_LVL_S && tsr_i) begin illegal_instr = 1'b1; // do not change privilege level if this is an illegal instruction - instruction_o.op = ADD; + instruction_o.op = ariane_pkg::ADD; end end // MRET 12'b11_0000_0010: begin - instruction_o.op = MRET; + instruction_o.op = ariane_pkg::MRET; // check privilege level, MRET can only be executed in M mode // otherwise we decode an illegal instruction if (priv_lvl_i inside {riscv::PRIV_LVL_U, riscv::PRIV_LVL_S}) @@ -131,23 +131,23 @@ module decoder ( end // DRET 12'b111_1011_0010: begin - instruction_o.op = DRET; + instruction_o.op = ariane_pkg::DRET; // check that we are in debug mode when executing this instruction illegal_instr = (!debug_mode_i) ? 1'b1 : 1'b0; end // WFI 12'b1_0000_0101: begin - if (ENABLE_WFI) instruction_o.op = WFI; + if (ENABLE_WFI) instruction_o.op = ariane_pkg::WFI; // if timeout wait is set, trap on an illegal instruction in S Mode // (after 0 cycles timeout) if (priv_lvl_i == riscv::PRIV_LVL_S && tw_i) begin illegal_instr = 1'b1; - instruction_o.op = ADD; + instruction_o.op = ariane_pkg::ADD; end // we don't support U mode interrupts so WFI is illegal in this context if (priv_lvl_i == riscv::PRIV_LVL_U) begin illegal_instr = 1'b1; - instruction_o.op = ADD; + instruction_o.op = ariane_pkg::ADD; end end // SFENCE.VMA @@ -156,7 +156,7 @@ module decoder ( // check privilege level, SFENCE.VMA can only be executed in M/S mode // otherwise decode an illegal instruction illegal_instr = (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) ? 1'b0 : 1'b1; - instruction_o.op = SFENCE_VMA; + instruction_o.op = ariane_pkg::SFENCE_VMA; // check TVM flag and intercept SFENCE.VMA call if necessary if (priv_lvl_i == riscv::PRIV_LVL_S && tvm_i) illegal_instr = 1'b1; @@ -167,32 +167,32 @@ module decoder ( // atomically swaps values in the CSR and integer register 3'b001: begin// CSRRW imm_select = IIMM; - instruction_o.op = CSR_WRITE; + instruction_o.op = ariane_pkg::CSR_WRITE; end // atomically set values in the CSR and write back to rd 3'b010: begin// CSRRS imm_select = IIMM; // this is just a read if (instr.itype.rs1 == 5'b0) - instruction_o.op = CSR_READ; + instruction_o.op = ariane_pkg::CSR_READ; else - instruction_o.op = CSR_SET; + instruction_o.op = ariane_pkg::CSR_SET; end // atomically clear values in the CSR and write back to rd 3'b011: begin// CSRRC imm_select = IIMM; // this is just a read if (instr.itype.rs1 == 5'b0) - instruction_o.op = CSR_READ; + instruction_o.op = ariane_pkg::CSR_READ; else - instruction_o.op = CSR_CLEAR; + instruction_o.op = ariane_pkg::CSR_CLEAR; end // use zimm and iimm 3'b101: begin// CSRRWI instruction_o.rs1[4:0] = instr.itype.rs1; imm_select = IIMM; instruction_o.use_zimm = 1'b1; - instruction_o.op = CSR_WRITE; + instruction_o.op = ariane_pkg::CSR_WRITE; end 3'b110: begin// CSRRSI instruction_o.rs1[4:0] = instr.itype.rs1; @@ -200,9 +200,9 @@ module decoder ( instruction_o.use_zimm = 1'b1; // this is just a read if (instr.itype.rs1 == 5'b0) - instruction_o.op = CSR_READ; + instruction_o.op = ariane_pkg::CSR_READ; else - instruction_o.op = CSR_SET; + instruction_o.op = ariane_pkg::CSR_SET; end 3'b111: begin// CSRRCI instruction_o.rs1[4:0] = instr.itype.rs1; @@ -210,9 +210,9 @@ module decoder ( instruction_o.use_zimm = 1'b1; // this is just a read if (instr.itype.rs1 == 5'b0) - instruction_o.op = CSR_READ; + instruction_o.op = ariane_pkg::CSR_READ; else - instruction_o.op = CSR_CLEAR; + instruction_o.op = ariane_pkg::CSR_CLEAR; end default: illegal_instr = 1'b1; endcase @@ -227,12 +227,12 @@ module decoder ( case (instr.stype.funct3) // FENCE // Currently implemented as a whole DCache flush boldly ignoring other things - 3'b000: instruction_o.op = FENCE; + 3'b000: instruction_o.op = ariane_pkg::FENCE; // FENCE.I 3'b001: begin if (instr.instr[31:20] != '0) illegal_instr = 1'b1; - instruction_o.op = FENCE_I; + instruction_o.op = ariane_pkg::FENCE_I; end default: illegal_instr = 1'b1; endcase @@ -262,38 +262,38 @@ module decoder ( // decode vectorial FP instruction unique case (instr.rvftype.vecfltop) 5'b00001 : begin - instruction_o.op = FADD; // vfadd.vfmt - Vectorial FP Addition + instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition instruction_o.rs1 = '0; // Operand A is set to 0 instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1 imm_select = IIMM; // Operand C is set to rs2 end 5'b00010 : begin - instruction_o.op = FSUB; // vfsub.vfmt - Vectorial FP Subtraction + instruction_o.op = ariane_pkg::FSUB; // vfsub.vfmt - Vectorial FP Subtraction instruction_o.rs1 = '0; // Operand A is set to 0 instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1 imm_select = IIMM; // Operand C is set to rs2 end - 5'b00011 : instruction_o.op = FMUL; // vfmul.vfmt - Vectorial FP Multiplication - 5'b00100 : instruction_o.op = FDIV; // vfdiv.vfmt - Vectorial FP Division + 5'b00011 : instruction_o.op = ariane_pkg::FMUL; // vfmul.vfmt - Vectorial FP Multiplication + 5'b00100 : instruction_o.op = ariane_pkg::FDIV; // vfdiv.vfmt - Vectorial FP Division 5'b00101 : begin - instruction_o.op = VFMIN; // vfmin.vfmt - Vectorial FP Minimum + instruction_o.op = ariane_pkg::VFMIN; // vfmin.vfmt - Vectorial FP Minimum check_fprm = 1'b0; // rounding mode irrelevant end 5'b00110 : begin - instruction_o.op = VFMAX; // vfmax.vfmt - Vectorial FP Maximum + instruction_o.op = ariane_pkg::VFMAX; // vfmax.vfmt - Vectorial FP Maximum check_fprm = 1'b0; // rounding mode irrelevant end 5'b00111 : begin - instruction_o.op = FSQRT; // vfsqrt.vfmt - Vectorial FP Square Root + instruction_o.op = ariane_pkg::FSQRT; // vfsqrt.vfmt - Vectorial FP Square Root allow_replication = 1'b0; // only one operand if (instr.rvftype.rs2 != 5'b00000) illegal_instr = 1'b1; // rs2 must be 0 end 5'b01000 : begin - instruction_o.op = FMADD; // vfmac.vfmt - Vectorial FP Multiply-Accumulate + instruction_o.op = ariane_pkg::FMADD; // vfmac.vfmt - Vectorial FP Multiply-Accumulate imm_select = SIMM; // rd into result field (upper bits don't matter) end 5'b01001 : begin - instruction_o.op = FMSUB; // vfmre.vfmt - Vectorial FP Multiply-Reduce + instruction_o.op = ariane_pkg::FMSUB; // vfmre.vfmt - Vectorial FP Multiply-Reduce imm_select = SIMM; // rd into result field (upper bits don't matter) end 5'b01100 : begin @@ -301,20 +301,20 @@ module decoder ( 5'b00000 : begin instruction_o.rs2 = instr.rvftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit if (instr.rvftype.repl) - instruction_o.op = FMV_X2F; // vfmv.vfmt.x - GPR to FPR Move + instruction_o.op = ariane_pkg::FMV_X2F; // vfmv.vfmt.x - GPR to FPR Move else - instruction_o.op = FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move + instruction_o.op = ariane_pkg::FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move check_fprm = 1'b0; // no rounding for moves end 5'b00001 : begin - instruction_o.op = FCLASS; // vfclass.vfmt - Vectorial FP Classify + instruction_o.op = ariane_pkg::FCLASS; // vfclass.vfmt - Vectorial FP Classify check_fprm = 1'b0; // no rounding for classification allow_replication = 1'b0; // R must not be set end - 5'b00010 : instruction_o.op = FCVT_F2I; // vfcvt.x.vfmt - Vectorial FP to Int Conversion - 5'b00011 : instruction_o.op = FCVT_I2F; // vfcvt.vfmt.x - Vectorial Int to FP Conversion + 5'b00010 : instruction_o.op = ariane_pkg::FCVT_F2I; // vfcvt.x.vfmt - Vectorial FP to Int Conversion + 5'b00011 : instruction_o.op = ariane_pkg::FCVT_I2F; // vfcvt.vfmt.x - Vectorial Int to FP Conversion 5'b001?? : begin - instruction_o.op = FCVT_F2F; // vfcvt.vfmt.vfmt - Vectorial FP to FP Conversion + instruction_o.op = ariane_pkg::FCVT_F2F; // vfcvt.vfmt.vfmt - Vectorial FP to FP Conversion instruction_o.rs2 = instr.rvftype.rd; // set rs2 = rd as target vector for conversion imm_select = IIMM; // rs2 holds part of the intruction // TODO CHECK R bit for valid fmt combinations @@ -333,42 +333,42 @@ module decoder ( end 5'b01101 : begin check_fprm = 1'b0; // no rounding for sign-injection - instruction_o.op = VFSGNJ; // vfsgnj.vfmt - Vectorial FP Sign Injection + instruction_o.op = ariane_pkg::VFSGNJ; // vfsgnj.vfmt - Vectorial FP Sign Injection end 5'b01110 : begin check_fprm = 1'b0; // no rounding for sign-injection - instruction_o.op = VFSGNJN; // vfsgnjn.vfmt - Vectorial FP Negated Sign Injection + instruction_o.op = ariane_pkg::VFSGNJN; // vfsgnjn.vfmt - Vectorial FP Negated Sign Injection end 5'b01111 : begin check_fprm = 1'b0; // no rounding for sign-injection - instruction_o.op = VFSGNJX; // vfsgnjx.vfmt - Vectorial FP XORed Sign Injection + instruction_o.op = ariane_pkg::VFSGNJX; // vfsgnjx.vfmt - Vectorial FP XORed Sign Injection end 5'b10000 : begin check_fprm = 1'b0; // no rounding for comparisons - instruction_o.op = VFEQ; // vfeq.vfmt - Vectorial FP Equality + instruction_o.op = ariane_pkg::VFEQ; // vfeq.vfmt - Vectorial FP Equality end 5'b10001 : begin check_fprm = 1'b0; // no rounding for comparisons - instruction_o.op = VFNE; // vfne.vfmt - Vectorial FP Non-Equality + instruction_o.op = ariane_pkg::VFNE; // vfne.vfmt - Vectorial FP Non-Equality end 5'b10010 : begin check_fprm = 1'b0; // no rounding for comparisons - instruction_o.op = VFLT; // vfle.vfmt - Vectorial FP Less Than + instruction_o.op = ariane_pkg::VFLT; // vfle.vfmt - Vectorial FP Less Than end 5'b10011 : begin check_fprm = 1'b0; // no rounding for comparisons - instruction_o.op = VFGE; // vfge.vfmt - Vectorial FP Greater or Equal + instruction_o.op = ariane_pkg::VFGE; // vfge.vfmt - Vectorial FP Greater or Equal end 5'b10100 : begin check_fprm = 1'b0; // no rounding for comparisons - instruction_o.op = VFLE; // vfle.vfmt - Vectorial FP Less or Equal + instruction_o.op = ariane_pkg::VFLE; // vfle.vfmt - Vectorial FP Less or Equal end 5'b10101 : begin check_fprm = 1'b0; // no rounding for comparisons - instruction_o.op = VFGT; // vfgt.vfmt - Vectorial FP Greater Than + instruction_o.op = ariane_pkg::VFGT; // vfgt.vfmt - Vectorial FP Greater Than end 5'b11000 : begin - instruction_o.op = VFCPKAB_S; // vfcpka/b.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, lowest 4 entries + instruction_o.op = ariane_pkg::VFCPKAB_S; // vfcpka/b.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, lowest 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) if (~RVF) illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 // check destination format @@ -391,7 +391,7 @@ module decoder ( endcase end 5'b11001 : begin - instruction_o.op = VFCPKCD_S; // vfcpkc/d.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, second 4 entries + instruction_o.op = ariane_pkg::VFCPKCD_S; // vfcpkc/d.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, second 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) if (~RVF) illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 // check destination format @@ -407,7 +407,7 @@ module decoder ( endcase end 5'b11010 : begin - instruction_o.op = VFCPKAB_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, lowest 4 entries + instruction_o.op = ariane_pkg::VFCPKAB_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, lowest 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) if (~RVD) illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 // check destination format @@ -430,7 +430,7 @@ module decoder ( endcase end 5'b11011 : begin - instruction_o.op = VFCPKCD_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, second 4 entries + instruction_o.op = ariane_pkg::VFCPKCD_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, second 4 entries imm_select = SIMM; // rd into result field (upper bits don't matter) if (~RVD) illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 // check destination format @@ -483,25 +483,25 @@ module decoder ( instruction_o.rd = instr.rtype.rd; unique case ({instr.rtype.funct7, instr.rtype.funct3}) - {7'b000_0000, 3'b000}: instruction_o.op = ADD; // Add - {7'b010_0000, 3'b000}: instruction_o.op = SUB; // Sub - {7'b000_0000, 3'b010}: instruction_o.op = SLTS; // Set Lower Than - {7'b000_0000, 3'b011}: instruction_o.op = SLTU; // Set Lower Than Unsigned - {7'b000_0000, 3'b100}: instruction_o.op = XORL; // Xor - {7'b000_0000, 3'b110}: instruction_o.op = ORL; // Or - {7'b000_0000, 3'b111}: instruction_o.op = ANDL; // And - {7'b000_0000, 3'b001}: instruction_o.op = SLL; // Shift Left Logical - {7'b000_0000, 3'b101}: instruction_o.op = SRL; // Shift Right Logical - {7'b010_0000, 3'b101}: instruction_o.op = SRA; // Shift Right Arithmetic + {7'b000_0000, 3'b000}: instruction_o.op = ariane_pkg::ADD; // Add + {7'b010_0000, 3'b000}: instruction_o.op = ariane_pkg::SUB; // Sub + {7'b000_0000, 3'b010}: instruction_o.op = ariane_pkg::SLTS; // Set Lower Than + {7'b000_0000, 3'b011}: instruction_o.op = ariane_pkg::SLTU; // Set Lower Than Unsigned + {7'b000_0000, 3'b100}: instruction_o.op = ariane_pkg::XORL; // Xor + {7'b000_0000, 3'b110}: instruction_o.op = ariane_pkg::ORL; // Or + {7'b000_0000, 3'b111}: instruction_o.op = ariane_pkg::ANDL; // And + {7'b000_0000, 3'b001}: instruction_o.op = ariane_pkg::SLL; // Shift Left Logical + {7'b000_0000, 3'b101}: instruction_o.op = ariane_pkg::SRL; // Shift Right Logical + {7'b010_0000, 3'b101}: instruction_o.op = ariane_pkg::SRA; // Shift Right Arithmetic // Multiplications - {7'b000_0001, 3'b000}: instruction_o.op = MUL; - {7'b000_0001, 3'b001}: instruction_o.op = MULH; - {7'b000_0001, 3'b010}: instruction_o.op = MULHSU; - {7'b000_0001, 3'b011}: instruction_o.op = MULHU; - {7'b000_0001, 3'b100}: instruction_o.op = DIV; - {7'b000_0001, 3'b101}: instruction_o.op = DIVU; - {7'b000_0001, 3'b110}: instruction_o.op = REM; - {7'b000_0001, 3'b111}: instruction_o.op = REMU; + {7'b000_0001, 3'b000}: instruction_o.op = ariane_pkg::MUL; + {7'b000_0001, 3'b001}: instruction_o.op = ariane_pkg::MULH; + {7'b000_0001, 3'b010}: instruction_o.op = ariane_pkg::MULHSU; + {7'b000_0001, 3'b011}: instruction_o.op = ariane_pkg::MULHU; + {7'b000_0001, 3'b100}: instruction_o.op = ariane_pkg::DIV; + {7'b000_0001, 3'b101}: instruction_o.op = ariane_pkg::DIVU; + {7'b000_0001, 3'b110}: instruction_o.op = ariane_pkg::REM; + {7'b000_0001, 3'b111}: instruction_o.op = ariane_pkg::REMU; default: begin illegal_instr = 1'b1; end @@ -519,17 +519,17 @@ module decoder ( instruction_o.rd[4:0] = instr.rtype.rd; unique case ({instr.rtype.funct7, instr.rtype.funct3}) - {7'b000_0000, 3'b000}: instruction_o.op = ADDW; // addw - {7'b010_0000, 3'b000}: instruction_o.op = SUBW; // subw - {7'b000_0000, 3'b001}: instruction_o.op = SLLW; // sllw - {7'b000_0000, 3'b101}: instruction_o.op = SRLW; // srlw - {7'b010_0000, 3'b101}: instruction_o.op = SRAW; // sraw + {7'b000_0000, 3'b000}: instruction_o.op = ariane_pkg::ADDW; // addw + {7'b010_0000, 3'b000}: instruction_o.op = ariane_pkg::SUBW; // subw + {7'b000_0000, 3'b001}: instruction_o.op = ariane_pkg::SLLW; // sllw + {7'b000_0000, 3'b101}: instruction_o.op = ariane_pkg::SRLW; // srlw + {7'b010_0000, 3'b101}: instruction_o.op = ariane_pkg::SRAW; // sraw // Multiplications - {7'b000_0001, 3'b000}: instruction_o.op = MULW; - {7'b000_0001, 3'b100}: instruction_o.op = DIVW; - {7'b000_0001, 3'b101}: instruction_o.op = DIVUW; - {7'b000_0001, 3'b110}: instruction_o.op = REMW; - {7'b000_0001, 3'b111}: instruction_o.op = REMUW; + {7'b000_0001, 3'b000}: instruction_o.op = ariane_pkg::MULW; + {7'b000_0001, 3'b100}: instruction_o.op = ariane_pkg::DIVW; + {7'b000_0001, 3'b101}: instruction_o.op = ariane_pkg::DIVUW; + {7'b000_0001, 3'b110}: instruction_o.op = ariane_pkg::REMW; + {7'b000_0001, 3'b111}: instruction_o.op = ariane_pkg::REMUW; default: illegal_instr = 1'b1; endcase end @@ -543,24 +543,24 @@ module decoder ( instruction_o.rd[4:0] = instr.itype.rd; unique case (instr.itype.funct3) - 3'b000: instruction_o.op = ADD; // Add Immediate - 3'b010: instruction_o.op = SLTS; // Set to one if Lower Than Immediate - 3'b011: instruction_o.op = SLTU; // Set to one if Lower Than Immediate Unsigned - 3'b100: instruction_o.op = XORL; // Exclusive Or with Immediate - 3'b110: instruction_o.op = ORL; // Or with Immediate - 3'b111: instruction_o.op = ANDL; // And with Immediate + 3'b000: instruction_o.op = ariane_pkg::ADD; // Add Immediate + 3'b010: instruction_o.op = ariane_pkg::SLTS; // Set to one if Lower Than Immediate + 3'b011: instruction_o.op = ariane_pkg::SLTU; // Set to one if Lower Than Immediate Unsigned + 3'b100: instruction_o.op = ariane_pkg::XORL; // Exclusive Or with Immediate + 3'b110: instruction_o.op = ariane_pkg::ORL; // Or with Immediate + 3'b111: instruction_o.op = ariane_pkg::ANDL; // And with Immediate 3'b001: begin - instruction_o.op = SLL; // Shift Left Logical by Immediate + instruction_o.op = ariane_pkg::SLL; // Shift Left Logical by Immediate if (instr.instr[31:26] != 6'b0) illegal_instr = 1'b1; end 3'b101: begin if (instr.instr[31:26] == 6'b0) - instruction_o.op = SRL; // Shift Right Logical by Immediate + instruction_o.op = ariane_pkg::SRL; // Shift Right Logical by Immediate else if (instr.instr[31:26] == 6'b010_000) - instruction_o.op = SRA; // Shift Right Arithmetically by Immediate + instruction_o.op = ariane_pkg::SRA; // Shift Right Arithmetically by Immediate else illegal_instr = 1'b1; end @@ -577,19 +577,19 @@ module decoder ( instruction_o.rd[4:0] = instr.itype.rd; unique case (instr.itype.funct3) - 3'b000: instruction_o.op = ADDW; // Add Immediate + 3'b000: instruction_o.op = ariane_pkg::ADDW; // Add Immediate 3'b001: begin - instruction_o.op = SLLW; // Shift Left Logical by Immediate + instruction_o.op = ariane_pkg::SLLW; // Shift Left Logical by Immediate if (instr.instr[31:25] != 7'b0) illegal_instr = 1'b1; end 3'b101: begin if (instr.instr[31:25] == 7'b0) - instruction_o.op = SRLW; // Shift Right Logical by Immediate + instruction_o.op = ariane_pkg::SRLW; // Shift Right Logical by Immediate else if (instr.instr[31:25] == 7'b010_0000) - instruction_o.op = SRAW; // Shift Right Arithmetically by Immediate + instruction_o.op = ariane_pkg::SRAW; // Shift Right Arithmetically by Immediate else illegal_instr = 1'b1; end @@ -607,10 +607,10 @@ module decoder ( instruction_o.rs2[4:0] = instr.stype.rs2; // determine store size unique case (instr.stype.funct3) - 3'b000: instruction_o.op = SB; - 3'b001: instruction_o.op = SH; - 3'b010: instruction_o.op = SW; - 3'b011: instruction_o.op = SD; + 3'b000: instruction_o.op = ariane_pkg::SB; + 3'b001: instruction_o.op = ariane_pkg::SH; + 3'b010: instruction_o.op = ariane_pkg::SW; + 3'b011: instruction_o.op = ariane_pkg::SD; default: illegal_instr = 1'b1; endcase end @@ -622,13 +622,13 @@ module decoder ( instruction_o.rd[4:0] = instr.itype.rd; // determine load size and signed type unique case (instr.itype.funct3) - 3'b000: instruction_o.op = LB; - 3'b001: instruction_o.op = LH; - 3'b010: instruction_o.op = LW; - 3'b100: instruction_o.op = LBU; - 3'b101: instruction_o.op = LHU; - 3'b110: instruction_o.op = LWU; - 3'b011: instruction_o.op = LD; + 3'b000: instruction_o.op = ariane_pkg::LB; + 3'b001: instruction_o.op = ariane_pkg::LH; + 3'b010: instruction_o.op = ariane_pkg::LW; + 3'b100: instruction_o.op = ariane_pkg::LBU; + 3'b101: instruction_o.op = ariane_pkg::LHU; + 3'b110: instruction_o.op = ariane_pkg::LWU; + 3'b011: instruction_o.op = ariane_pkg::LD; default: illegal_instr = 1'b1; endcase end @@ -645,13 +645,13 @@ module decoder ( // determine store size unique case (instr.stype.funct3) // Only process instruction if corresponding extension is active (static) - 3'b000: if (XF8) instruction_o.op = FSB; + 3'b000: if (XF8) instruction_o.op = ariane_pkg::FSB; else illegal_instr = 1'b1; - 3'b001: if (XF16 | XF16ALT) instruction_o.op = FSH; + 3'b001: if (XF16 | XF16ALT) instruction_o.op = ariane_pkg::FSH; else illegal_instr = 1'b1; - 3'b010: if (RVF) instruction_o.op = FSW; + 3'b010: if (RVF) instruction_o.op = ariane_pkg::FSW; else illegal_instr = 1'b1; - 3'b011: if (RVD) instruction_o.op = FSD; + 3'b011: if (RVD) instruction_o.op = ariane_pkg::FSD; else illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -668,13 +668,13 @@ module decoder ( // determine load size unique case (instr.itype.funct3) // Only process instruction if corresponding extension is active (static) - 3'b000: if (XF8) instruction_o.op = FLB; + 3'b000: if (XF8) instruction_o.op = ariane_pkg::FLB; else illegal_instr = 1'b1; - 3'b001: if (XF16 | XF16ALT) instruction_o.op = FLH; + 3'b001: if (XF16 | XF16ALT) instruction_o.op = ariane_pkg::FLH; else illegal_instr = 1'b1; - 3'b010: if (RVF) instruction_o.op = FLW; + 3'b010: if (RVF) instruction_o.op = ariane_pkg::FLW; else illegal_instr = 1'b1; - 3'b011: if (RVD) instruction_o.op = FLD; + 3'b011: if (RVD) instruction_o.op = ariane_pkg::FLD; else illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -698,10 +698,10 @@ module decoder ( check_fprm = 1'b1; // select the correct fused operation unique case (instr.r4type.opcode) - default: instruction_o.op = FMADD; // fmadd.fmt - FP Fused multiply-add - riscv::OpcodeMsub: instruction_o.op = FMSUB; // fmsub.fmt - FP Fused multiply-subtract - riscv::OpcodeNmsub: instruction_o.op = FNMSUB; // fnmsub.fmt - FP Negated fused multiply-subtract - riscv::OpcodeNmadd: instruction_o.op = FNMADD; // fnmadd.fmt - FP Negated fused multiply-add + default: instruction_o.op = ariane_pkg::FMADD; // fmadd.fmt - FP Fused multiply-add + riscv::OpcodeMsub: instruction_o.op = ariane_pkg::FMSUB; // fmsub.fmt - FP Fused multiply-subtract + riscv::OpcodeNmsub: instruction_o.op = ariane_pkg::FNMSUB; // fnmsub.fmt - FP Negated fused multiply-subtract + riscv::OpcodeNmadd: instruction_o.op = ariane_pkg::FNMADD; // fnmadd.fmt - FP Negated fused multiply-add endcase // determine fp format @@ -751,26 +751,26 @@ module decoder ( // decode FP instruction unique case (instr.rftype.funct5) 5'b00000: begin - instruction_o.op = FADD; // fadd.fmt - FP Addition + instruction_o.op = ariane_pkg::FADD; // fadd.fmt - FP Addition instruction_o.rs1 = '0; // Operand A is set to 0 instruction_o.rs2 = instr.rftype.rs1; // Operand B is set to rs1 imm_select = IIMM; // Operand C is set to rs2 end 5'b00001: begin - instruction_o.op = FSUB; // fsub.fmt - FP Subtraction + instruction_o.op = ariane_pkg::FSUB; // fsub.fmt - FP Subtraction instruction_o.rs1 = '0; // Operand A is set to 0 instruction_o.rs2 = instr.rftype.rs1; // Operand B is set to rs1 imm_select = IIMM; // Operand C is set to rs2 end - 5'b00010: instruction_o.op = FMUL; // fmul.fmt - FP Multiplication - 5'b00011: instruction_o.op = FDIV; // fdiv.fmt - FP Division + 5'b00010: instruction_o.op = ariane_pkg::FMUL; // fmul.fmt - FP Multiplication + 5'b00011: instruction_o.op = ariane_pkg::FDIV; // fdiv.fmt - FP Division 5'b01011: begin - instruction_o.op = FSQRT; // fsqrt.fmt - FP Square Root + instruction_o.op = ariane_pkg::FSQRT; // fsqrt.fmt - FP Square Root // rs2 must be zero if (instr.rftype.rs2 != 5'b00000) illegal_instr = 1'b1; end 5'b00100: begin - instruction_o.op = FSGNJ; // fsgn{j[n]/jx}.fmt - FP Sign Injection + instruction_o.op = ariane_pkg::FSGNJ; // fsgn{j[n]/jx}.fmt - FP Sign Injection check_fprm = 1'b0; // instruction encoded in rm, do the check here if (XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) if (!(instr.rftype.rm inside {[3'b000:3'b010], [3'b100:3'b110]})) @@ -781,7 +781,7 @@ module decoder ( end end 5'b00101: begin - instruction_o.op = FMIN_MAX; // fmin/fmax.fmt - FP Minimum / Maximum + instruction_o.op = ariane_pkg::FMIN_MAX; // fmin/fmax.fmt - FP Minimum / Maximum check_fprm = 1'b0; // instruction encoded in rm, do the check here if (XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) if (!(instr.rftype.rm inside {[3'b000:3'b001], [3'b100:3'b101]})) @@ -792,7 +792,7 @@ module decoder ( end end 5'b01000: begin - instruction_o.op = FCVT_F2F; // fcvt.fmt.fmt - FP to FP Conversion + instruction_o.op = ariane_pkg::FCVT_F2F; // fcvt.fmt.fmt - FP to FP Conversion instruction_o.rs2 = instr.rvftype.rs1; // tie rs2 to rs1 to be safe (vectors use rs2) imm_select = IIMM; // rs2 holds part of the intruction if (instr.rftype.rs2[24:23]) illegal_instr = 1'b1; // bits [22:20] used, other bits must be 0 @@ -808,7 +808,7 @@ module decoder ( endcase end 5'b10100: begin - instruction_o.op = FCMP; // feq/flt/fle.fmt - FP Comparisons + instruction_o.op = ariane_pkg::FCMP; // feq/flt/fle.fmt - FP Comparisons check_fprm = 1'b0; // instruction encoded in rm, do the check here if (XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) if (!(instr.rftype.rm inside {[3'b000:3'b010], [3'b100:3'b110]})) @@ -819,12 +819,12 @@ module decoder ( end end 5'b11000: begin - instruction_o.op = FCVT_F2I; // fcvt.ifmt.fmt - FP to Int Conversion + instruction_o.op = ariane_pkg::FCVT_F2I; // fcvt.ifmt.fmt - FP to Int Conversion imm_select = IIMM; // rs2 holds part of the instruction if (instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 end 5'b11010: begin - instruction_o.op = FCVT_I2F; // fcvt.fmt.ifmt - Int to FP Conversion + instruction_o.op = ariane_pkg::FCVT_I2F; // fcvt.fmt.ifmt - Int to FP Conversion imm_select = IIMM; // rs2 holds part of the instruction if (instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 end @@ -832,15 +832,15 @@ module decoder ( instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit check_fprm = 1'b0; // instruction encoded in rm, do the check here if (instr.rftype.rm == 3'b000 || (XF16ALT && instr.rftype.rm == 3'b100)) // FP16ALT has separate encoding - instruction_o.op = FMV_F2X; // fmv.ifmt.fmt - FPR to GPR Move + instruction_o.op = ariane_pkg::FMV_F2X; // fmv.ifmt.fmt - FPR to GPR Move else if (instr.rftype.rm == 3'b001 || (XF16ALT && instr.rftype.rm == 3'b101)) // FP16ALT has separate encoding - instruction_o.op = FCLASS; // fclass.fmt - FP Classify + instruction_o.op = ariane_pkg::FCLASS; // fclass.fmt - FP Classify else illegal_instr = 1'b1; // rs2 must be zero if (instr.rftype.rs2 != 5'b00000) illegal_instr = 1'b1; end 5'b11110: begin - instruction_o.op = FMV_X2F; // fmv.fmt.ifmt - GPR to FPR Move + instruction_o.op = ariane_pkg::FMV_X2F; // fmv.fmt.ifmt - GPR to FPR Move instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit check_fprm = 1'b0; // instruction encoded in rm, do the check here if (!(instr.rftype.rm == 3'b000 || (XF16ALT && instr.rftype.rm == 3'b100))) @@ -901,39 +901,39 @@ module decoder ( // words if (RVA && instr.stype.funct3 == 3'h2) begin unique case (instr.instr[31:27]) - 5'h0: instruction_o.op = AMO_ADDW; - 5'h1: instruction_o.op = AMO_SWAPW; + 5'h0: instruction_o.op = ariane_pkg::AMO_ADDW; + 5'h1: instruction_o.op = ariane_pkg::AMO_SWAPW; 5'h2: begin - instruction_o.op = AMO_LRW; + instruction_o.op = ariane_pkg::AMO_LRW; if (instr.atype.rs2 != 0) illegal_instr = 1'b1; end - 5'h3: instruction_o.op = AMO_SCW; - 5'h4: instruction_o.op = AMO_XORW; - 5'h8: instruction_o.op = AMO_ORW; - 5'hC: instruction_o.op = AMO_ANDW; - 5'h10: instruction_o.op = AMO_MINW; - 5'h14: instruction_o.op = AMO_MAXW; - 5'h18: instruction_o.op = AMO_MINWU; - 5'h1C: instruction_o.op = AMO_MAXWU; + 5'h3: instruction_o.op = ariane_pkg::AMO_SCW; + 5'h4: instruction_o.op = ariane_pkg::AMO_XORW; + 5'h8: instruction_o.op = ariane_pkg::AMO_ORW; + 5'hC: instruction_o.op = ariane_pkg::AMO_ANDW; + 5'h10: instruction_o.op = ariane_pkg::AMO_MINW; + 5'h14: instruction_o.op = ariane_pkg::AMO_MAXW; + 5'h18: instruction_o.op = ariane_pkg::AMO_MINWU; + 5'h1C: instruction_o.op = ariane_pkg::AMO_MAXWU; default: illegal_instr = 1'b1; endcase // double words end else if (RVA && instr.stype.funct3 == 3'h3) begin unique case (instr.instr[31:27]) - 5'h0: instruction_o.op = AMO_ADDD; - 5'h1: instruction_o.op = AMO_SWAPD; + 5'h0: instruction_o.op = ariane_pkg::AMO_ADDD; + 5'h1: instruction_o.op = ariane_pkg::AMO_SWAPD; 5'h2: begin - instruction_o.op = AMO_LRD; + instruction_o.op = ariane_pkg::AMO_LRD; if (instr.atype.rs2 != 0) illegal_instr = 1'b1; end - 5'h3: instruction_o.op = AMO_SCD; - 5'h4: instruction_o.op = AMO_XORD; - 5'h8: instruction_o.op = AMO_ORD; - 5'hC: instruction_o.op = AMO_ANDD; - 5'h10: instruction_o.op = AMO_MIND; - 5'h14: instruction_o.op = AMO_MAXD; - 5'h18: instruction_o.op = AMO_MINDU; - 5'h1C: instruction_o.op = AMO_MAXDU; + 5'h3: instruction_o.op = ariane_pkg::AMO_SCD; + 5'h4: instruction_o.op = ariane_pkg::AMO_XORD; + 5'h8: instruction_o.op = ariane_pkg::AMO_ORD; + 5'hC: instruction_o.op = ariane_pkg::AMO_ANDD; + 5'h10: instruction_o.op = ariane_pkg::AMO_MIND; + 5'h14: instruction_o.op = ariane_pkg::AMO_MAXD; + 5'h18: instruction_o.op = ariane_pkg::AMO_MINDU; + 5'h1C: instruction_o.op = ariane_pkg::AMO_MAXDU; default: illegal_instr = 1'b1; endcase end else begin @@ -953,12 +953,12 @@ module decoder ( is_control_flow_instr_o = 1'b1; case (instr.stype.funct3) - 3'b000: instruction_o.op = EQ; - 3'b001: instruction_o.op = NE; - 3'b100: instruction_o.op = LTS; - 3'b101: instruction_o.op = GES; - 3'b110: instruction_o.op = LTU; - 3'b111: instruction_o.op = GEU; + 3'b000: instruction_o.op = ariane_pkg::EQ; + 3'b001: instruction_o.op = ariane_pkg::NE; + 3'b100: instruction_o.op = ariane_pkg::LTS; + 3'b101: instruction_o.op = ariane_pkg::GES; + 3'b110: instruction_o.op = ariane_pkg::LTU; + 3'b111: instruction_o.op = ariane_pkg::GEU; default: begin is_control_flow_instr_o = 1'b0; illegal_instr = 1'b1; @@ -968,7 +968,7 @@ module decoder ( // Jump and link register riscv::OpcodeJalr: begin instruction_o.fu = CTRL_FLOW; - instruction_o.op = JALR; + instruction_o.op = ariane_pkg::JALR; instruction_o.rs1[4:0] = instr.itype.rs1; imm_select = IIMM; instruction_o.rd[4:0] = instr.itype.rd; diff --git a/src/fpu b/src/fpu index 857ae9282..2f30a43cb 160000 --- a/src/fpu +++ b/src/fpu @@ -1 +1 @@ -Subproject commit 857ae928242d8afc40b4fea3f9d4a0cdf4ebe7c5 +Subproject commit 2f30a43cbb1a79f86b651b08542028b2394ab432 diff --git a/src/load_unit.sv b/src/load_unit.sv index a6761edb9..b54f34bdb 100644 --- a/src/load_unit.sv +++ b/src/load_unit.sv @@ -300,11 +300,11 @@ module load_unit ( // prepare these signals for faster selection in the next cycle - assign signed_d = load_data_d.operator inside {LW, LH, LB}; - assign fp_sign_d = load_data_d.operator inside {FLW, FLH, FLB}; - assign idx_d = (load_data_d.operator inside {LW, FLW}) ? load_data_d.address_offset + 3 : - (load_data_d.operator inside {LH, FLH}) ? load_data_d.address_offset + 1 : - load_data_d.address_offset; + assign signed_d = load_data_d.operator inside {ariane_pkg::LW, ariane_pkg::LH, ariane_pkg::LB}; + assign fp_sign_d = load_data_d.operator inside {ariane_pkg::FLW, ariane_pkg::FLH, ariane_pkg::FLB}; + assign idx_d = (load_data_d.operator inside {ariane_pkg::LW, ariane_pkg::FLW}) ? load_data_d.address_offset + 3 : + (load_data_d.operator inside {ariane_pkg::LH, ariane_pkg::FLH}) ? load_data_d.address_offset + 1 : + load_data_d.address_offset; assign sign_bits = { req_port_i.data_rdata[63], @@ -323,9 +323,9 @@ module load_unit ( // result mux always_comb begin unique case (load_data_q.operator) - LW, LWU, FLW: result_o = {{32{sign_bit}}, shifted_data[31:0]}; - LH, LHU, FLH: result_o = {{48{sign_bit}}, shifted_data[15:0]}; - LB, LBU, FLB: result_o = {{56{sign_bit}}, shifted_data[7:0]}; + ariane_pkg::LW, ariane_pkg::LWU, ariane_pkg::FLW: result_o = {{32{sign_bit}}, shifted_data[31:0]}; + ariane_pkg::LH, ariane_pkg::LHU, ariane_pkg::FLH: result_o = {{48{sign_bit}}, shifted_data[15:0]}; + ariane_pkg::LB, ariane_pkg::LBU, ariane_pkg::FLB: result_o = {{56{sign_bit}}, shifted_data[7:0]}; default: result_o = shifted_data; endcase end @@ -351,11 +351,11 @@ module load_unit ( `ifndef VERILATOR // check invalid offsets addr_offset0: assert property (@(posedge clk_i) disable iff (~rst_ni) - valid_o |-> (load_data_q.operator inside {LW, LWU}) |-> load_data_q.address_offset < 5) else $fatal (1,"invalid address offset used with {LW, LWU}"); + valid_o |-> (load_data_q.operator inside {ariane_pkg::LW, ariane_pkg::LWU}) |-> load_data_q.address_offset < 5) else $fatal (1,"invalid address offset used with {LW, LWU}"); addr_offset1: assert property (@(posedge clk_i) disable iff (~rst_ni) - valid_o |-> (load_data_q.operator inside {LH, LHU}) |-> load_data_q.address_offset < 7) else $fatal (1,"invalid address offset used with {LH, LHU}"); + valid_o |-> (load_data_q.operator inside {ariane_pkg::LH, ariane_pkg::LHU}) |-> load_data_q.address_offset < 7) else $fatal (1,"invalid address offset used with {LH, LHU}"); addr_offset2: assert property (@(posedge clk_i) disable iff (~rst_ni) - valid_o |-> (load_data_q.operator inside {LB, LBU}) |-> load_data_q.address_offset < 8) else $fatal (1,"invalid address offset used with {LB, LBU}"); + valid_o |-> (load_data_q.operator inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> load_data_q.address_offset < 8) else $fatal (1,"invalid address offset used with {LB, LBU}"); `endif //pragma translate_on diff --git a/src/util/exception_trace_item.svh b/src/util/ex_trace_item.svh similarity index 98% rename from src/util/exception_trace_item.svh rename to src/util/ex_trace_item.svh index 87ff4ae06..ca8f68d95 100644 --- a/src/util/exception_trace_item.svh +++ b/src/util/ex_trace_item.svh @@ -12,7 +12,7 @@ // Date: 17.06.2017 // Description: Instruction tracer single exception item -class exception_trace_item; +class ex_trace_item; // contains a human readable form of the cause value string cause_s; logic [63:0] cause; @@ -71,4 +71,4 @@ class exception_trace_item; return s; endfunction -endclass : exception_trace_item +endclass : ex_trace_item diff --git a/src/util/instruction_trace_item.svh b/src/util/instr_trace_item.svh similarity index 54% rename from src/util/instruction_trace_item.svh rename to src/util/instr_trace_item.svh index 0d04c3ae2..48ec3058f 100644 --- a/src/util/instruction_trace_item.svh +++ b/src/util/instr_trace_item.svh @@ -12,11 +12,20 @@ // Date: 30.05.2017 // Description: Instruction tracer single instruction item -class instruction_trace_item; +function string printPCexpr(input logic [63:0] imm); + // check if the sign bit is set + if ($signed(imm) > 0) begin + return $sformatf("pc + %0d", $signed(imm)); + end else begin + return $sformatf("pc - %0d", $signed(-imm)); + end +endfunction + +class instr_trace_item; // keep a couple of general purpose information inside this instruction item time simtime; longint unsigned cycle; - scoreboard_entry_t sbe; + ariane_pkg::scoreboard_entry_t sbe; logic [31:0] pc; logic [31:0] instr; logic [63:0] gp_reg_file [32]; @@ -29,13 +38,13 @@ class instruction_trace_item; logic [63:0] result; logic [63:0] paddr; string priv_lvl; - bp_resolve_t bp; + ariane_pkg::bp_resolve_t bp; logic [4:0] rs1, rs2, rs3, rd; // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information - function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32], - logic [63:0] fp_reg_file [32], logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); + function new (time simtime, longint unsigned cycle, ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32], + logic [63:0] fp_reg_file [32], logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); this.simtime = simtime; this.cycle = cycle; this.pc = sbe.pc; @@ -186,172 +195,172 @@ class instruction_trace_item; case (instr) inside // Aliases - 32'h00_00_00_13: s = this.printMnemonic("nop"); + instr_tracer_pkg::INSTR_NOP: s = this.printMnemonic("nop"); // Regular opcodes - INSTR_LUI: s = this.printUInstr("lui"); - INSTR_AUIPC: s = this.printUInstr("auipc"); - INSTR_JAL: s = this.printJump("jal"); - INSTR_JALR: s = this.printJump("jalr"); + instr_tracer_pkg::INSTR_LUI: s = this.printUInstr("lui"); + instr_tracer_pkg::INSTR_AUIPC: s = this.printUInstr("auipc"); + instr_tracer_pkg::INSTR_JAL: s = this.printJump("jal"); + instr_tracer_pkg::INSTR_JALR: s = this.printJump("jalr"); // BRANCH - INSTR_BEQZ: s = this.printSBInstr("beqz"); - INSTR_BEQ: s = this.printSBInstr("beq"); - INSTR_BNEZ: s = this.printSBInstr("bnez"); - INSTR_BNE: s = this.printSBInstr("bne"); - INSTR_BLTZ: s = this.printSBInstr("bltz"); - INSTR_BLT: s = this.printSBInstr("blt"); - INSTR_BGEZ: s = this.printSBInstr("bgez"); - INSTR_BGE: s = this.printSBInstr("bge"); - INSTR_BLTU: s = this.printSBInstr("bltu"); - INSTR_BGEU: s = this.printSBInstr("bgeu"); + instr_tracer_pkg::INSTR_BEQZ: s = this.printSBInstr("beqz"); + instr_tracer_pkg::INSTR_BEQ: s = this.printSBInstr("beq"); + instr_tracer_pkg::INSTR_BNEZ: s = this.printSBInstr("bnez"); + instr_tracer_pkg::INSTR_BNE: s = this.printSBInstr("bne"); + instr_tracer_pkg::INSTR_BLTZ: s = this.printSBInstr("bltz"); + instr_tracer_pkg::INSTR_BLT: s = this.printSBInstr("blt"); + instr_tracer_pkg::INSTR_BGEZ: s = this.printSBInstr("bgez"); + instr_tracer_pkg::INSTR_BGE: s = this.printSBInstr("bge"); + instr_tracer_pkg::INSTR_BLTU: s = this.printSBInstr("bltu"); + instr_tracer_pkg::INSTR_BGEU: s = this.printSBInstr("bgeu"); // OPIMM - INSTR_LI: s = this.printIInstr("li"); - INSTR_ADDI: s = this.printIInstr("addi"); - INSTR_SLTI: s = this.printIInstr("slti"); - INSTR_SLTIU: s = this.printIInstr("sltiu"); - INSTR_XORI: s = this.printIInstr("xori"); - INSTR_ORI: s = this.printIInstr("ori"); - INSTR_ANDI: s = this.printIInstr("andi"); - INSTR_SLLI: s = this.printIuInstr("slli"); - INSTR_SRLI: s = this.printIuInstr("srli"); - INSTR_SRAI: s = this.printIuInstr("srai"); + instr_tracer_pkg::INSTR_LI: s = this.printIInstr("li"); + instr_tracer_pkg::INSTR_ADDI: s = this.printIInstr("addi"); + instr_tracer_pkg::INSTR_SLTI: s = this.printIInstr("slti"); + instr_tracer_pkg::INSTR_SLTIU: s = this.printIInstr("sltiu"); + instr_tracer_pkg::INSTR_XORI: s = this.printIInstr("xori"); + instr_tracer_pkg::INSTR_ORI: s = this.printIInstr("ori"); + instr_tracer_pkg::INSTR_ANDI: s = this.printIInstr("andi"); + instr_tracer_pkg::INSTR_SLLI: s = this.printIuInstr("slli"); + instr_tracer_pkg::INSTR_SRLI: s = this.printIuInstr("srli"); + instr_tracer_pkg::INSTR_SRAI: s = this.printIuInstr("srai"); // OPIMM32 - INSTR_ADDIW: s = this.printIInstr("addiw"); - INSTR_SLLIW: s = this.printIuInstr("slliw"); - INSTR_SRLIW: s = this.printIuInstr("srliw"); - INSTR_SRAIW: s = this.printIuInstr("sraiw"); + instr_tracer_pkg::INSTR_ADDIW: s = this.printIInstr("addiw"); + instr_tracer_pkg::INSTR_SLLIW: s = this.printIuInstr("slliw"); + instr_tracer_pkg::INSTR_SRLIW: s = this.printIuInstr("srliw"); + instr_tracer_pkg::INSTR_SRAIW: s = this.printIuInstr("sraiw"); // OP - INSTR_ADD: s = this.printRInstr("add"); - INSTR_SUB: s = this.printRInstr("sub"); - INSTR_SLL: s = this.printRInstr("sll"); - INSTR_SLT: s = this.printRInstr("slt"); - INSTR_SLTU: s = this.printRInstr("sltu"); - INSTR_XOR: s = this.printRInstr("xor"); - INSTR_SRL: s = this.printRInstr("srl"); - INSTR_SRA: s = this.printRInstr("sra"); - INSTR_OR: s = this.printRInstr("or"); - INSTR_AND: s = this.printRInstr("and"); - INSTR_MUL: s = this.printMulInstr(1'b0); + instr_tracer_pkg::INSTR_ADD: s = this.printRInstr("add"); + instr_tracer_pkg::INSTR_SUB: s = this.printRInstr("sub"); + instr_tracer_pkg::INSTR_SLL: s = this.printRInstr("sll"); + instr_tracer_pkg::INSTR_SLT: s = this.printRInstr("slt"); + instr_tracer_pkg::INSTR_SLTU: s = this.printRInstr("sltu"); + instr_tracer_pkg::INSTR_XOR: s = this.printRInstr("xor"); + instr_tracer_pkg::INSTR_SRL: s = this.printRInstr("srl"); + instr_tracer_pkg::INSTR_SRA: s = this.printRInstr("sra"); + instr_tracer_pkg::INSTR_OR: s = this.printRInstr("or"); + instr_tracer_pkg::INSTR_AND: s = this.printRInstr("and"); + instr_tracer_pkg::INSTR_MUL: s = this.printMulInstr(1'b0); // OP32 - INSTR_ADDW: s = this.printRInstr("addw"); - INSTR_SUBW: s = this.printRInstr("subw"); - INSTR_SLLW: s = this.printRInstr("sllw"); - INSTR_SRLW: s = this.printRInstr("srlw"); - INSTR_SRAW: s = this.printRInstr("sraw"); - INSTR_MULW: s = this.printMulInstr(1'b1); + instr_tracer_pkg::INSTR_ADDW: s = this.printRInstr("addw"); + instr_tracer_pkg::INSTR_SUBW: s = this.printRInstr("subw"); + instr_tracer_pkg::INSTR_SLLW: s = this.printRInstr("sllw"); + instr_tracer_pkg::INSTR_SRLW: s = this.printRInstr("srlw"); + instr_tracer_pkg::INSTR_SRAW: s = this.printRInstr("sraw"); + instr_tracer_pkg::INSTR_MULW: s = this.printMulInstr(1'b1); // FP - INSTR_FMADD: s = this.printR4Instr("fmadd"); - INSTR_FMSUB: s = this.printR4Instr("fmsub"); - INSTR_FNSMSUB: s = this.printR4Instr("fnmsub"); - INSTR_FNMADD: s = this.printR4Instr("fnmadd"); + instr_tracer_pkg::INSTR_FMADD: s = this.printR4Instr("fmadd"); + instr_tracer_pkg::INSTR_FMSUB: s = this.printR4Instr("fmsub"); + instr_tracer_pkg::INSTR_FNSMSUB: s = this.printR4Instr("fnmsub"); + instr_tracer_pkg::INSTR_FNMADD: s = this.printR4Instr("fnmadd"); - INSTR_FADD: s = this.printRFBCInstr("fadd", 1'b1); - INSTR_FSUB: s = this.printRFBCInstr("fsub", 1'b1); - INSTR_FMUL: s = this.printRFInstr("fmul", 1'b1); - INSTR_FDIV: s = this.printRFInstr("fdiv", 1'b1); - INSTR_FSQRT: s = this.printRFInstr1Op("fsqrt", 1'b1); - INSTR_FSGNJ: s = this.printRFInstr("fsgnj", 1'b0); - INSTR_FSGNJN: s = this.printRFInstr("fsgnjn", 1'b0); - INSTR_FSGNJX: s = this.printRFInstr("fsgnjx", 1'b0); - INSTR_FMIN: s = this.printRFInstr("fmin", 1'b0); - INSTR_FMAX: s = this.printRFInstr("fmax", 1'b0); - INSTR_FLE: s = this.printRFInstr("fle", 1'b0); - INSTR_FLT: s = this.printRFInstr("flt", 1'b0); - INSTR_FEQ: s = this.printRFInstr("feq", 1'b0); + instr_tracer_pkg::INSTR_FADD: s = this.printRFBCInstr("fadd", 1'b1); + instr_tracer_pkg::INSTR_FSUB: s = this.printRFBCInstr("fsub", 1'b1); + instr_tracer_pkg::INSTR_FMUL: s = this.printRFInstr("fmul", 1'b1); + instr_tracer_pkg::INSTR_FDIV: s = this.printRFInstr("fdiv", 1'b1); + instr_tracer_pkg::INSTR_FSQRT: s = this.printRFInstr1Op("fsqrt", 1'b1); + instr_tracer_pkg::INSTR_FSGNJ: s = this.printRFInstr("fsgnj", 1'b0); + instr_tracer_pkg::INSTR_FSGNJN: s = this.printRFInstr("fsgnjn", 1'b0); + instr_tracer_pkg::INSTR_FSGNJX: s = this.printRFInstr("fsgnjx", 1'b0); + instr_tracer_pkg::INSTR_FMIN: s = this.printRFInstr("fmin", 1'b0); + instr_tracer_pkg::INSTR_FMAX: s = this.printRFInstr("fmax", 1'b0); + instr_tracer_pkg::INSTR_FLE: s = this.printRFInstr("fle", 1'b0); + instr_tracer_pkg::INSTR_FLT: s = this.printRFInstr("flt", 1'b0); + instr_tracer_pkg::INSTR_FEQ: s = this.printRFInstr("feq", 1'b0); - INSTR_FCLASS: s = this.printRFInstr1Op("fclass", 1'b0); + instr_tracer_pkg::INSTR_FCLASS: s = this.printRFInstr1Op("fclass", 1'b0); - INSTR_FCVT_F2F, - INSTR_FMV_F2X, - INSTR_FMV_X2F, - INSTR_FCVT_F2I, - INSTR_FCVT_I2F: s = this.printFpSpecialInstr(); // these are a mess to do nicely + instr_tracer_pkg::INSTR_FCVT_F2F, + instr_tracer_pkg::INSTR_FMV_F2X, + instr_tracer_pkg::INSTR_FMV_X2F, + instr_tracer_pkg::INSTR_FCVT_F2I, + instr_tracer_pkg::INSTR_FCVT_I2F: s = this.printFpSpecialInstr(); // these are a mess to do nicely // FENCE - INSTR_FENCE: s = this.printMnemonic("fence"); - INSTR_FENCEI: s = this.printMnemonic("fence.i"); + instr_tracer_pkg::INSTR_FENCE: s = this.printMnemonic("fence"); + instr_tracer_pkg::INSTR_FENCEI: s = this.printMnemonic("fence.i"); // SYSTEM (CSR manipulation) - INSTR_CSRW: s = this.printCSRInstr("csrw"); - INSTR_CSRRW: s = this.printCSRInstr("csrrw"); - INSTR_CSRR: s = this.printCSRInstr("csrr"); - INSTR_CSRRS: s = this.printCSRInstr("csrrs"); - INSTR_CSRS: s = this.printCSRInstr("csrs"); - INSTR_CSRRC: s = this.printCSRInstr("csrrc"); - INSTR_CSRC: s = this.printCSRInstr("csrc"); + instr_tracer_pkg::INSTR_CSRW: s = this.printCSRInstr("csrw"); + instr_tracer_pkg::INSTR_CSRRW: s = this.printCSRInstr("csrrw"); + instr_tracer_pkg::INSTR_CSRR: s = this.printCSRInstr("csrr"); + instr_tracer_pkg::INSTR_CSRRS: s = this.printCSRInstr("csrrs"); + instr_tracer_pkg::INSTR_CSRS: s = this.printCSRInstr("csrs"); + instr_tracer_pkg::INSTR_CSRRC: s = this.printCSRInstr("csrrc"); + instr_tracer_pkg::INSTR_CSRC: s = this.printCSRInstr("csrc"); - INSTR_CSRWI: s = this.printCSRInstr("csrwi"); - INSTR_CSRRWI: s = this.printCSRInstr("csrrwi"); - INSTR_CSRSI: s = this.printCSRInstr("csrsi"); - INSTR_CSRRSI: s = this.printCSRInstr("csrrsi"); - INSTR_CSRCI: s = this.printCSRInstr("csrci"); - INSTR_CSRRCI: s = this.printCSRInstr("csrrci"); + instr_tracer_pkg::INSTR_CSRWI: s = this.printCSRInstr("csrwi"); + instr_tracer_pkg::INSTR_CSRRWI: s = this.printCSRInstr("csrrwi"); + instr_tracer_pkg::INSTR_CSRSI: s = this.printCSRInstr("csrsi"); + instr_tracer_pkg::INSTR_CSRRSI: s = this.printCSRInstr("csrrsi"); + instr_tracer_pkg::INSTR_CSRCI: s = this.printCSRInstr("csrci"); + instr_tracer_pkg::INSTR_CSRRCI: s = this.printCSRInstr("csrrci"); // SYSTEM (others) - INSTR_ECALL: s = this.printMnemonic("ecall"); - INSTR_EBREAK: s = this.printMnemonic("ebreak"); - INSTR_MRET: s = this.printMnemonic("mret"); - INSTR_SRET: s = this.printMnemonic("sret"); - INSTR_DRET: s = this.printMnemonic("dret"); - INSTR_WFI: s = this.printMnemonic("wfi"); - INSTR_SFENCE: s = this.printMnemonic("sfence.vma"); + instr_tracer_pkg::INSTR_ECALL: s = this.printMnemonic("ecall"); + instr_tracer_pkg::INSTR_EBREAK: s = this.printMnemonic("ebreak"); + instr_tracer_pkg::INSTR_MRET: s = this.printMnemonic("mret"); + instr_tracer_pkg::INSTR_SRET: s = this.printMnemonic("sret"); + instr_tracer_pkg::INSTR_DRET: s = this.printMnemonic("dret"); + instr_tracer_pkg::INSTR_WFI: s = this.printMnemonic("wfi"); + instr_tracer_pkg::INSTR_SFENCE: s = this.printMnemonic("sfence.vma"); // loads and stores - LB: s = this.printLoadInstr("lb"); - LH: s = this.printLoadInstr("lh"); - LW: s = this.printLoadInstr("lw"); - LD: s = this.printLoadInstr("ld"); - LBU: s = this.printLoadInstr("lbu"); - LHU: s = this.printLoadInstr("lhu"); - LWU: s = this.printLoadInstr("lwu"); - FLW: s = this.printLoadInstr("flw"); - FLD: s = this.printLoadInstr("fld"); - FLQ: s = this.printLoadInstr("flq"); - FSW: s = this.printLoadInstr("fsw"); - FSD: s = this.printLoadInstr("fsd"); - FSQ: s = this.printLoadInstr("fsq"); - SB: s = this.printStoreInstr("sb"); - SH: s = this.printStoreInstr("sh"); - SW: s = this.printStoreInstr("sw"); - SD: s = this.printStoreInstr("sd"); - FSW: s = this.printStoreInstr("fsw"); - FSD: s = this.printStoreInstr("fsd"); - FSQ: s = this.printStoreInstr("fsq"); - INSTR_AMO: s = this.printAMOInstr(); + instr_tracer_pkg::LB: s = this.printLoadInstr("lb"); + instr_tracer_pkg::LH: s = this.printLoadInstr("lh"); + instr_tracer_pkg::LW: s = this.printLoadInstr("lw"); + instr_tracer_pkg::LD: s = this.printLoadInstr("ld"); + instr_tracer_pkg::LBU: s = this.printLoadInstr("lbu"); + instr_tracer_pkg::LHU: s = this.printLoadInstr("lhu"); + instr_tracer_pkg::LWU: s = this.printLoadInstr("lwu"); + instr_tracer_pkg::FLW: s = this.printLoadInstr("flw"); + instr_tracer_pkg::FLD: s = this.printLoadInstr("fld"); + instr_tracer_pkg::FLQ: s = this.printLoadInstr("flq"); + instr_tracer_pkg::FSW: s = this.printLoadInstr("fsw"); + instr_tracer_pkg::FSD: s = this.printLoadInstr("fsd"); + instr_tracer_pkg::FSQ: s = this.printLoadInstr("fsq"); + instr_tracer_pkg::SB: s = this.printStoreInstr("sb"); + instr_tracer_pkg::SH: s = this.printStoreInstr("sh"); + instr_tracer_pkg::SW: s = this.printStoreInstr("sw"); + instr_tracer_pkg::SD: s = this.printStoreInstr("sd"); + instr_tracer_pkg::FSW: s = this.printStoreInstr("fsw"); + instr_tracer_pkg::FSD: s = this.printStoreInstr("fsd"); + instr_tracer_pkg::FSQ: s = this.printStoreInstr("fsq"); + instr_tracer_pkg::INSTR_AMO: s = this.printAMOInstr(); // Compressed Instructions - C_FLD: s = this.printLoadInstr("c.fld"); - C_LW: s = this.printLoadInstr("c.lw"); - C_LD: s = this.printLoadInstr("c.ld"); - C_LWSP: s = this.printLoadInstr("c.lwsp"); - C_LDSP: s = this.printLoadInstr("c.ldsp"); - C_FLDSP: s = this.printLoadInstr("c.fldsp"); - C_SDSP: s = this.printStoreInstr("c.sdsp"); - C_SWSP: s = this.printStoreInstr("c.swsp"); - C_FSDSP: s = this.printStoreInstr("c.fsdsp"); - C_SW: s = this.printStoreInstr("c.sw"); - C_SD: s = this.printStoreInstr("c.sd"); - C_FSD: s = this.printStoreInstr("c.fsd"); - C_J: s = this.printJump("c.j"); - C_JR: s = this.printJump("c.jr"); - C_JALR: s = this.printJump("c.jalr"); - C_MV: s = this.printRInstr("c.mv"); - C_ADD: s = this.printRInstr("c.add"); - C_BEQZ: s = this.printSBInstr("c.beqz"); - C_BNEZ: s = this.printSBInstr("c.bnez"); - C_LUI: s = this.printUInstr("c.lui"); - C_LI: s = this.printIInstr("c.li"); - C_ADDI: s = this.printIInstr("c.addi"); - C_ADDI16SP: s = this.printIInstr("c.addi16sp"); - C_ADDIW: s = this.printIInstr("c.addiw"); - C_SLLI: s = this.printIInstr("c.slli"); - C_SRLI: s = this.printIInstr("c.srli"); - C_SRAI: s = this.printIInstr("c.srai"); - C_ANDI: s = this.printIInstr("c.andi"); - C_ADDI4SPN: s = this.printIInstr("c.addi4spn"); - C_SUB: s = this.printRInstr("c.sub"); - C_XOR: s = this.printRInstr("c.xor"); - C_OR: s = this.printRInstr("c.or"); - C_AND: s = this.printRInstr("c.and"); - C_SUBW: s = this.printRInstr("c.subw"); - C_ADDW: s = this.printRInstr("c.addw"); - C_NOP: s = this.printMnemonic("c.nop"); - C_EBREAK: s = this.printMnemonic("c.ebreak"); - default: s = this.printMnemonic("INVALID"); + instr_tracer_pkg::C_FLD: s = this.printLoadInstr("c.fld"); + instr_tracer_pkg::C_LW: s = this.printLoadInstr("c.lw"); + instr_tracer_pkg::C_LD: s = this.printLoadInstr("c.ld"); + instr_tracer_pkg::C_LWSP: s = this.printLoadInstr("c.lwsp"); + instr_tracer_pkg::C_LDSP: s = this.printLoadInstr("c.ldsp"); + instr_tracer_pkg::C_FLDSP: s = this.printLoadInstr("c.fldsp"); + instr_tracer_pkg::C_SDSP: s = this.printStoreInstr("c.sdsp"); + instr_tracer_pkg::C_SWSP: s = this.printStoreInstr("c.swsp"); + instr_tracer_pkg::C_FSDSP: s = this.printStoreInstr("c.fsdsp"); + instr_tracer_pkg::C_SW: s = this.printStoreInstr("c.sw"); + instr_tracer_pkg::C_SD: s = this.printStoreInstr("c.sd"); + instr_tracer_pkg::C_FSD: s = this.printStoreInstr("c.fsd"); + instr_tracer_pkg::C_J: s = this.printJump("c.j"); + instr_tracer_pkg::C_JR: s = this.printJump("c.jr"); + instr_tracer_pkg::C_JALR: s = this.printJump("c.jalr"); + instr_tracer_pkg::C_MV: s = this.printRInstr("c.mv"); + instr_tracer_pkg::C_ADD: s = this.printRInstr("c.add"); + instr_tracer_pkg::C_BEQZ: s = this.printSBInstr("c.beqz"); + instr_tracer_pkg::C_BNEZ: s = this.printSBInstr("c.bnez"); + instr_tracer_pkg::C_LUI: s = this.printUInstr("c.lui"); + instr_tracer_pkg::C_LI: s = this.printIInstr("c.li"); + instr_tracer_pkg::C_ADDI: s = this.printIInstr("c.addi"); + instr_tracer_pkg::C_ADDI16SP: s = this.printIInstr("c.addi16sp"); + instr_tracer_pkg::C_ADDIW: s = this.printIInstr("c.addiw"); + instr_tracer_pkg::C_SLLI: s = this.printIInstr("c.slli"); + instr_tracer_pkg::C_SRLI: s = this.printIInstr("c.srli"); + instr_tracer_pkg::C_SRAI: s = this.printIInstr("c.srai"); + instr_tracer_pkg::C_ANDI: s = this.printIInstr("c.andi"); + instr_tracer_pkg::C_ADDI4SPN: s = this.printIInstr("c.addi4spn"); + instr_tracer_pkg::C_SUB: s = this.printRInstr("c.sub"); + instr_tracer_pkg::C_XOR: s = this.printRInstr("c.xor"); + instr_tracer_pkg::C_OR: s = this.printRInstr("c.or"); + instr_tracer_pkg::C_AND: s = this.printRInstr("c.and"); + instr_tracer_pkg::C_SUBW: s = this.printRInstr("c.subw"); + instr_tracer_pkg::C_ADDW: s = this.printRInstr("c.addw"); + instr_tracer_pkg::C_NOP: s = this.printMnemonic("c.nop"); + instr_tracer_pkg::C_EBREAK: s = this.printMnemonic("c.ebreak"); + default: s = this.printMnemonic("INVALID"); endcase s = $sformatf("%8dns %8d %s %h %h %h %-36s", simtime, @@ -384,13 +393,43 @@ class instruction_trace_item; case (instr) inside // check of the instruction was a load or store - C_SDSP, C_SWSP, C_FSWSP, C_FSDSP, C_SW, C_SD, C_FSW, C_FSD, - SB, SH, SW, SD, FSW, FSD, FSQ: begin + instr_tracer_pkg::C_SDSP, + instr_tracer_pkg::C_SWSP, + instr_tracer_pkg::C_FSWSP, + instr_tracer_pkg::C_FSDSP, + instr_tracer_pkg::C_SW, + instr_tracer_pkg::C_SD, + instr_tracer_pkg::C_FSW, + instr_tracer_pkg::C_FSD, + instr_tracer_pkg::SB, + instr_tracer_pkg::SH, + instr_tracer_pkg::SW, + instr_tracer_pkg::SD, + instr_tracer_pkg::FSW, + instr_tracer_pkg::FSD, + instr_tracer_pkg::FSQ: begin logic [63:0] vaddress = gp_reg_file[read_regs[1]] + this.imm; s = $sformatf("%s VA: %x PA: %x", s, vaddress, this.paddr); end - C_FLD, C_FLW, C_LW, C_LD, C_LWSP, C_LDSP, C_FLWSP, C_FLDSP, - LB, LH, LW, LD, LBU, LHU, LWU, FLW, FLD, FLQ: begin + + instr_tracer_pkg::C_FLD, + instr_tracer_pkg::C_FLW, + instr_tracer_pkg::C_LW, + instr_tracer_pkg::C_LD, + instr_tracer_pkg::C_LWSP, + instr_tracer_pkg::C_LDSP, + instr_tracer_pkg::C_FLWSP, + instr_tracer_pkg::C_FLDSP, + instr_tracer_pkg::LB, + instr_tracer_pkg::LH, + instr_tracer_pkg::LW, + instr_tracer_pkg::LD, + instr_tracer_pkg::LBU, + instr_tracer_pkg::LHU, + instr_tracer_pkg::LWU, + instr_tracer_pkg::FLW, + instr_tracer_pkg::FLD, + instr_tracer_pkg::FLQ: begin logic [63:0] vaddress = gp_reg_file[read_regs[0]] + this.imm; s = $sformatf("%s VA: %x PA: %x", s, vaddress, this.paddr); end @@ -426,44 +465,44 @@ class instruction_trace_item; function string printRFBCInstr(input string mnemonic, input bit use_rnd); result_regs.push_back(rd); - result_fpr.push_back(is_rd_fpr(sbe.op)); + result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); read_regs.push_back(rs2); - read_fpr.push_back(is_rs2_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op)); read_regs.push_back(sbe.result[4:0]); - read_fpr.push_back(is_imm_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_imm_fpr(sbe.op)); if (use_rnd && instr[14:12]!=3'b111) - return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]), fpRmToStr(instr[14:12])); + return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]), fpRmToStr(instr[14:12])); else - return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0])); + return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0])); endfunction // printRFInstr function string printRFInstr(input string mnemonic, input bit use_rnd); result_regs.push_back(rd); - result_fpr.push_back(is_rd_fpr(sbe.op)); + result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); read_regs.push_back(rs1); - read_fpr.push_back(is_rs1_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op)); read_regs.push_back(rs2); - read_fpr.push_back(is_rs2_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op)); if (use_rnd && instr[14:12]!=3'b111) - return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), fpRmToStr(instr[14:12])); + return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), fpRmToStr(instr[14:12])); else - return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2)); + return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2)); endfunction // printRFInstr function string printRFInstr1Op(input string mnemonic, input bit use_rnd); result_regs.push_back(rd); - result_fpr.push_back(is_rd_fpr(sbe.op)); + result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); read_regs.push_back(rs1); - read_fpr.push_back(is_rs1_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op)); if (use_rnd && instr[14:12]!=3'b111) - return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), fpRmToStr(instr[14:12])); + return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), fpRmToStr(instr[14:12])); else - return $sformatf("%-12s %4s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1)); + return $sformatf("%-12s %4s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1)); endfunction // printRFInstr1Op function string printR4Instr(input string mnemonic); @@ -483,16 +522,16 @@ class instruction_trace_item; function string printFpSpecialInstr(); result_regs.push_back(rd); - result_fpr.push_back(is_rd_fpr(sbe.op)); + result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); read_regs.push_back(rs1); - read_fpr.push_back(is_rs1_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op)); case (sbe.op) - FCVT_F2F : return $sformatf("%-12s %4s, %s, %s", $sformatf("fcvt.%s.%s", fpFmtToStr(instr[26:25]), fpFmtToStr(instr[21:20])), fpRegAddrToStr(rd), fpRegAddrToStr(rs1), fpRmToStr(instr[14:12])); - FCVT_F2I : return $sformatf("%-12s %4s, %s, %s", $sformatf("fcvt.%s.%s", intFmtToStr(instr[21:20]), fpFmtToStr(instr[26:25])), regAddrToStr(rd), fpRegAddrToStr(rs1), fpRmToStr(instr[14:12])); - FCVT_I2F : return $sformatf("%-12s %4s, %s, %s", $sformatf("fcvt.%s.%s", fpFmtToStr(instr[26:25]), intFmtToStr(instr[21:20])), fpRegAddrToStr(rd), regAddrToStr(rs1), fpRmToStr(instr[14:12])); - FMV_F2X : return $sformatf("%-12s %4s, %s", $sformatf("fmv.x.%s", fmvFpFmtToStr(instr[26:25])), regAddrToStr(rd), fpRegAddrToStr(rs1)); - FMV_X2F : return $sformatf("%-12s %4s, %s", $sformatf("fmv.%s.x", fmvFpFmtToStr(instr[26:25])), fpRegAddrToStr(rd), regAddrToStr(rs1)); + instr_tracer_pkg::INSTR_FCVT_F2F : return $sformatf("%-12s %4s, %s, %s", $sformatf("fcvt.%s.%s", fpFmtToStr(instr[26:25]), fpFmtToStr(instr[21:20])), fpRegAddrToStr(rd), fpRegAddrToStr(rs1), fpRmToStr(instr[14:12])); + instr_tracer_pkg::INSTR_FCVT_F2I : return $sformatf("%-12s %4s, %s, %s", $sformatf("fcvt.%s.%s", intFmtToStr(instr[21:20]), fpFmtToStr(instr[26:25])), regAddrToStr(rd), fpRegAddrToStr(rs1), fpRmToStr(instr[14:12])); + instr_tracer_pkg::INSTR_FCVT_I2F : return $sformatf("%-12s %4s, %s, %s", $sformatf("fcvt.%s.%s", fpFmtToStr(instr[26:25]), intFmtToStr(instr[21:20])), fpRegAddrToStr(rd), regAddrToStr(rs1), fpRmToStr(instr[14:12])); + instr_tracer_pkg::INSTR_FMV_F2X : return $sformatf("%-12s %4s, %s", $sformatf("fmv.x.%s", fmvFpFmtToStr(instr[26:25])), regAddrToStr(rd), fpRegAddrToStr(rs1)); + instr_tracer_pkg::INSTR_FMV_X2F : return $sformatf("%-12s %4s, %s", $sformatf("fmv.%s.x", fmvFpFmtToStr(instr[26:25])), fpRegAddrToStr(rd), regAddrToStr(rs1)); endcase endfunction @@ -594,7 +633,7 @@ class instruction_trace_item; function string printLoadInstr(input string mnemonic); result_regs.push_back(rd); - result_fpr.push_back(is_rd_fpr(sbe.op)); + result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); read_regs.push_back(rs1); read_fpr.push_back(1'b0); // save the immediate for calculating the virtual address @@ -608,7 +647,7 @@ class instruction_trace_item; function string printStoreInstr(input string mnemonic); read_regs.push_back(rs2); - read_fpr.push_back(is_rs2_fpr(sbe.op)); + read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op)); read_regs.push_back(rs1); read_fpr.push_back(1'b0); // save the immediate for calculating the virtual address @@ -682,12 +721,3 @@ class instruction_trace_item; return this.printRInstr(s); endfunction endclass - - function string printPCexpr(input logic [63:0] imm); - // check if the sign bit is set - if ($signed(imm) > 0) begin - return $sformatf("pc + %0d", $signed(imm)); - end else begin - return $sformatf("pc - %0d", $signed(-imm)); - end - endfunction diff --git a/src/util/instruction_tracer.sv b/src/util/instr_tracer.sv similarity index 81% rename from src/util/instruction_tracer.sv rename to src/util/instr_tracer.sv index 0f551f46e..434e2de76 100644 --- a/src/util/instruction_tracer.sv +++ b/src/util/instr_tracer.sv @@ -12,18 +12,16 @@ // Date: 16.05.2017 // Description: Instruction Tracer Main Class -import ariane_pkg::*; //pragma translate_off import uvm_pkg::*; `include "uvm_macros.svh" -`include "instruction_tracer_defines.svh" -`include "instruction_trace_item.svh" -`include "exception_trace_item.svh" +`include "ex_trace_item.svh" +`include "instr_trace_item.svh" //pragma translate_on -module instruction_tracer ( - instruction_tracer_if tracer_if, - input logic[63:0] hart_id_i +module instr_tracer ( + instr_tracer_if tracer_if, + input logic[63:0] hart_id_i ); // keep the decoded instructions in a queue @@ -31,10 +29,10 @@ module instruction_tracer ( // keep the issued instructions in a queue logic [31:0] issue_queue [$]; // issue scoreboard entries - scoreboard_entry_t issue_sbe_queue [$]; - scoreboard_entry_t issue_sbe; + ariane_pkg::scoreboard_entry_t issue_sbe_queue [$]; + ariane_pkg::scoreboard_entry_t issue_sbe; // store resolved branches, get (mis-)predictions - bp_resolve_t bp [$]; + ariane_pkg::bp_resolve_t bp [$]; // shadow copy of the register files logic [63:0] gp_reg_file [32]; logic [63:0] fp_reg_file [32]; @@ -54,18 +52,18 @@ module instruction_tracer ( $display("[TRACER] Output filename is: %s", fn); f = $fopen(fn,"w"); - if (ENABLE_SPIKE_COMMIT_LOG) commit_log = $fopen(fn_commit_log, "w"); + if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG) commit_log = $fopen(fn_commit_log, "w"); endfunction : create_file task trace(); automatic logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction; - automatic scoreboard_entry_t commit_instruction; + automatic ariane_pkg::scoreboard_entry_t commit_instruction; // initialize register 0 gp_reg_file = '{default:0}; fp_reg_file = '{default:0}; forever begin - automatic bp_resolve_t bp_instruction = '0; + automatic ariane_pkg::bp_resolve_t bp_instruction = '0; // new cycle, we are only interested if reset is de-asserted @(tracer_if.pck iff tracer_if.pck.rstn); // increment clock tick @@ -88,7 +86,7 @@ module instruction_tracer ( issue_instruction = decode_queue.pop_front(); issue_queue.push_back(issue_instruction); // also save the scoreboard entry to a separate issue queue - issue_sbe_queue.push_back(scoreboard_entry_t'(tracer_if.pck.issue_sbe)); + issue_sbe_queue.push_back(ariane_pkg::scoreboard_entry_t'(tracer_if.pck.issue_sbe)); end // -------------------- @@ -113,23 +111,23 @@ module instruction_tracer ( // we are committing an instruction for (int i = 0; i < 2; i++) begin if (tracer_if.pck.commit_ack[i]) begin - commit_instruction = scoreboard_entry_t'(tracer_if.pck.commit_instr[i]); + commit_instruction = ariane_pkg::scoreboard_entry_t'(tracer_if.pck.commit_instr[i]); issue_commit_instruction = issue_queue.pop_front(); issue_sbe = issue_sbe_queue.pop_front(); // check if the instruction retiring is a load or store, get the physical address accordingly - if (tracer_if.pck.commit_instr[i].fu == LOAD) + if (tracer_if.pck.commit_instr[i].fu == ariane_pkg::LOAD) address_mapping = load_mapping.pop_front(); - else if (tracer_if.pck.commit_instr[i].fu == STORE) + else if (tracer_if.pck.commit_instr[i].fu == ariane_pkg::STORE) address_mapping = store_mapping.pop_front(); - if (tracer_if.pck.commit_instr[i].fu == CTRL_FLOW) + if (tracer_if.pck.commit_instr[i].fu == ariane_pkg::CTRL_FLOW) bp_instruction = bp.pop_front(); // the scoreboards issue entry still contains the immediate value as a result // check if the write back is valid, if not we need to source the result from the register file // as the most recent version of this register will be there. if (tracer_if.pck.we_gpr[i] || tracer_if.pck.we_fpr[i]) begin printInstr(issue_sbe, issue_commit_instruction, tracer_if.pck.wdata[i], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction); - end else if (is_rd_fpr(commit_instruction.op)) begin + end else if (ariane_pkg::is_rd_fpr(commit_instruction.op)) begin printInstr(issue_sbe, issue_commit_instruction, fp_reg_file[commit_instruction.rd], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction); end else begin printInstr(issue_sbe, issue_commit_instruction, gp_reg_file[commit_instruction.rd], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction); @@ -186,19 +184,19 @@ module instruction_tracer ( bp = {}; endfunction - function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); - automatic instruction_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); + function void printInstr(ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); + automatic instr_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); // print instruction to console automatic string print_instr = iti.printInstr(); - if (ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin - $fwrite(commit_log, riscv::spikeCommitLog(sbe.pc, priv_lvl, instr, sbe.rd, result, is_rd_fpr(sbe.op))); + if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin + $fwrite(commit_log, riscv::spikeCommitLog(sbe.pc, priv_lvl, instr, sbe.rd, result, ariane_pkg::is_rd_fpr(sbe.op))); end uvm_report_info( "Tracer", print_instr, UVM_HIGH); $fwrite(f, {print_instr, "\n"}); endfunction function void printException(logic [63:0] pc, logic [63:0] cause, logic [63:0] tval); - automatic exception_trace_item eti = new (pc, cause, tval); + automatic ex_trace_item eti = new (pc, cause, tval); automatic string print_ex = eti.printException(); uvm_report_info( "Tracer", print_ex, UVM_HIGH); $fwrite(f, {print_ex, "\n"}); @@ -206,7 +204,7 @@ module instruction_tracer ( function void close(); if (f) $fclose(f); - if (ENABLE_SPIKE_COMMIT_LOG && commit_log) $fclose(commit_log); + if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG && commit_log) $fclose(commit_log); endfunction @@ -220,4 +218,4 @@ module instruction_tracer ( close(); end -endmodule : instruction_tracer +endmodule : instr_tracer diff --git a/src/util/instruction_tracer_if.sv b/src/util/instr_tracer_if.sv similarity index 84% rename from src/util/instruction_tracer_if.sv rename to src/util/instr_tracer_if.sv index cc458d48a..18e8cfb56 100644 --- a/src/util/instruction_tracer_if.sv +++ b/src/util/instr_tracer_if.sv @@ -12,10 +12,9 @@ // Date: 16.05.2017 // Description: Instruction Tracer Interface -import ariane_pkg::*; `ifndef INSTR_TRACER_IF_SV `define INSTR_TRACER_IF_SV -interface instruction_tracer_if ( +interface instr_tracer_if ( input clk ); @@ -27,16 +26,16 @@ interface instruction_tracer_if ( logic fetch_valid; logic fetch_ack; // Issue stage - logic issue_ack; // issue acknowledged - scoreboard_entry_t issue_sbe; // issue scoreboard entry + logic issue_ack; // issue acknowledged + ariane_pkg::scoreboard_entry_t issue_sbe; // issue scoreboard entry // WB stage logic [1:0][4:0] waddr; logic [1:0][63:0] wdata; logic [1:0] we_gpr; logic [1:0] we_fpr; // commit stage - scoreboard_entry_t [1:0] commit_instr; // commit instruction - logic [1:0] commit_ack; + ariane_pkg::scoreboard_entry_t [1:0] commit_instr; // commit instruction + logic [1:0] commit_ack; // address translation // stores logic st_valid; @@ -46,9 +45,9 @@ interface instruction_tracer_if ( logic ld_kill; logic [63:0] ld_paddr; // misprediction - bp_resolve_t resolve_branch; + ariane_pkg::bp_resolve_t resolve_branch; // exceptions - exception_t exception; + ariane_pkg::exception_t exception; // current privilege level riscv::priv_lvl_t priv_lvl; logic debug_mode; diff --git a/src/util/instruction_tracer_defines.svh b/src/util/instruction_tracer_defines.svh deleted file mode 100644 index cac47d8f2..000000000 --- a/src/util/instruction_tracer_defines.svh +++ /dev/null @@ -1,194 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Author: Florian Zaruba, ETH Zurich -// Date: 16.05.2017 -// Description: Instruction Tracer Defines - -parameter INSTR_LUI = { 25'b?, riscv::OpcodeLui }; -parameter INSTR_AUIPC = { 25'b?, riscv::OpcodeAuipc }; -parameter INSTR_JAL = { 25'b?, riscv::OpcodeJal }; -parameter INSTR_JALR = { 17'b?, 3'b000, 5'b?, riscv::OpcodeJalr }; -// BRANCH -parameter INSTR_BEQZ = { 7'b?, 5'b0, 5'b?, 3'b000, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BEQ = { 7'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BNEZ = { 7'b?, 5'b0, 5'b?, 3'b001, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BNE = { 7'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BLTZ = { 7'b?, 5'b0, 5'b?, 3'b100, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BLT = { 7'b?, 5'b?, 5'b?, 3'b100, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BGEZ = { 7'b?, 5'b0, 5'b?, 3'b101, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BGE = { 7'b?, 5'b?, 5'b?, 3'b101, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BLTU = { 7'b?, 5'b?, 5'b?, 3'b110, 5'b?, riscv::OpcodeBranch }; -parameter INSTR_BGEU = { 7'b?, 5'b?, 5'b?, 3'b111, 5'b?, riscv::OpcodeBranch }; - -// OP-IMM -parameter INSTR_LI = { 12'b?, 5'b0, 3'b000, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_ADDI = { 17'b?, 3'b000, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_SLTI = { 17'b?, 3'b010, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_XORI = { 17'b?, 3'b100, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_ORI = { 17'b?, 3'b110, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_ANDI = { 17'b?, 3'b111, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_SLLI = { 6'b000000, 11'b?, 3'b001, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_SRLI = { 6'b000000, 11'b?, 3'b101, 5'b?, riscv::OpcodeOpImm }; -parameter INSTR_SRAI = { 6'b010000, 11'b?, 3'b101, 5'b?, riscv::OpcodeOpImm }; - -// OP-IMM-32 -parameter INSTR_ADDIW = { 17'b?, 3'b000, 5'b?, riscv::OpcodeOpImm32 }; -parameter INSTR_SLLIW = { 7'b0000000, 10'b?, 3'b001, 5'b?, riscv::OpcodeOpImm32 }; -parameter INSTR_SRLIW = { 7'b0000000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOpImm32 }; -parameter INSTR_SRAIW = { 7'b0100000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOpImm32 }; - -// OP -parameter INSTR_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp }; -parameter INSTR_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp }; -parameter INSTR_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, riscv::OpcodeOp }; -parameter INSTR_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, riscv::OpcodeOp }; -parameter INSTR_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, riscv::OpcodeOp }; -parameter INSTR_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, riscv::OpcodeOp }; -parameter INSTR_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp }; -parameter INSTR_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp }; -parameter INSTR_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, riscv::OpcodeOp }; -parameter INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, riscv::OpcodeOp }; -parameter INSTR_MUL = { 7'b0000001, 10'b?, 3'b???, 5'b?, riscv::OpcodeOp }; - -// OP32 -parameter INSTR_ADDW = { 7'b0000000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp32 }; -parameter INSTR_SUBW = { 7'b0100000, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp32 }; -parameter INSTR_SLLW = { 7'b0000000, 10'b?, 3'b001, 5'b?, riscv::OpcodeOp32 }; -parameter INSTR_SRLW = { 7'b0000000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp32 }; -parameter INSTR_SRAW = { 7'b0100000, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp32 }; -parameter INSTR_MULW = { 7'b0000001, 10'b?, 3'b???, 5'b?, riscv::OpcodeOp32 }; - -// MISC-MEM -parameter INSTR_FENCE = { 4'b0, 8'b?, 13'b0, riscv::OpcodeMiscMem }; -parameter INSTR_FENCEI = { 17'b0, 3'b001, 5'b0, riscv::OpcodeMiscMem }; - -// SYSTEM -parameter INSTR_CSRW = { 12'b?, 5'b?, 3'b001, 5'b0, riscv::OpcodeSystem }; -parameter INSTR_CSRRW = { 12'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeSystem }; -parameter INSTR_CSRR = { 12'b?, 5'b0, 3'b010, 5'b?, riscv::OpcodeSystem }; -parameter INSTR_CSRRS = { 12'b?, 5'b?, 3'b010, 5'b?, riscv::OpcodeSystem }; -parameter INSTR_CSRS = { 12'b?, 5'b?, 3'b010, 5'b0, riscv::OpcodeSystem }; -parameter INSTR_CSRRC = { 12'b?, 5'b?, 3'b011, 5'b?, riscv::OpcodeSystem }; -parameter INSTR_CSRC = { 12'b?, 5'b?, 3'b011, 5'b0, riscv::OpcodeSystem }; - -parameter INSTR_CSRWI = { 17'b?, 3'b101, 5'b0, riscv::OpcodeSystem }; -parameter INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, riscv::OpcodeSystem }; -parameter INSTR_CSRSI = { 17'b?, 3'b110, 5'b0, riscv::OpcodeSystem }; -parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, riscv::OpcodeSystem }; -parameter INSTR_CSRCI = { 17'b?, 3'b111, 5'b0, riscv::OpcodeSystem }; -parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, riscv::OpcodeSystem }; - -parameter INSTR_ECALL = { 12'b000000000000, 13'b0, riscv::OpcodeSystem }; -parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, riscv::OpcodeSystem }; -parameter INSTR_MRET = { 12'b001100000010, 13'b0, riscv::OpcodeSystem }; -parameter INSTR_SRET = { 12'b000100000010, 13'b0, riscv::OpcodeSystem }; -parameter INSTR_DRET = { 12'b011110110010, 13'b0, riscv::OpcodeSystem }; -parameter INSTR_WFI = { 12'b000100000101, 13'b0, riscv::OpcodeSystem }; -parameter INSTR_SFENCE = { 12'b0001001?????, 13'b?, riscv::OpcodeSystem }; - -// RV32M -parameter INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, riscv::OpcodeOp }; -parameter INSTR_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, riscv::OpcodeOp }; -parameter INSTR_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, riscv::OpcodeOp }; -parameter INSTR_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, riscv::OpcodeOp }; -parameter INSTR_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, riscv::OpcodeOp }; - -// RVFD -parameter INSTR_FMADD = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeMadd}; -parameter INSTR_FMSUB = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeMsub}; -parameter INSTR_FNSMSUB = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeNmsub}; -parameter INSTR_FNMADD = { 5'b?, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeNmadd}; - -parameter INSTR_FADD = { 5'b00000, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FSUB = { 5'b00001, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FMUL = { 5'b00010, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FDIV = { 5'b00011, 2'b?, 5'b?, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FSQRT = { 5'b01011, 2'b?, 5'b0, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FSGNJ = { 5'b00100, 2'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FSGNJN = { 5'b00100, 2'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FSGNJX = { 5'b00100, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FMIN = { 5'b00101, 2'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FMAX = { 5'b00101, 2'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FLE = { 5'b10100, 2'b?, 5'b?, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FLT = { 5'b10100, 2'b?, 5'b?, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FEQ = { 5'b10100, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, riscv::OpcodeOpFp}; - -parameter INSTR_FCVT_F2F = { 5'b01000, 2'b?, 5'b000??, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FMV_F2X = { 5'b11100, 2'b?, 5'b0, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FCLASS = { 5'b11100, 2'b?, 5'b0, 5'b?, 3'b001, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FMV_X2F = { 5'b11110, 2'b?, 5'b0, 5'b?, 3'b000, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FCVT_F2I = { 5'b11000, 2'b?, 5'b000??, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; -parameter INSTR_FCVT_I2F = { 5'b11010, 2'b?, 5'b000??, 5'b?, 3'b?, 5'b?, riscv::OpcodeOpFp}; - -// A -parameter INSTR_AMO = {25'b?, riscv::OpcodeAmo }; - -// Load/Stores -parameter [31:0] LB = 32'b?????????????????000?????0000011; -parameter [31:0] LH = 32'b?????????????????001?????0000011; -parameter [31:0] LW = 32'b?????????????????010?????0000011; -parameter [31:0] LD = 32'b?????????????????011?????0000011; -parameter [31:0] LBU = 32'b?????????????????100?????0000011; -parameter [31:0] LHU = 32'b?????????????????101?????0000011; -parameter [31:0] LWU = 32'b?????????????????110?????0000011; -parameter [31:0] FLW = 32'b?????????????????010?????0000111; -parameter [31:0] FLD = 32'b?????????????????011?????0000111; -parameter [31:0] FLQ = 32'b?????????????????100?????0000111; -parameter [31:0] SB = 32'b?????????????????000?????0100011; -parameter [31:0] SH = 32'b?????????????????001?????0100011; -parameter [31:0] SW = 32'b?????????????????010?????0100011; -parameter [31:0] SD = 32'b?????????????????011?????0100011; -parameter [31:0] FSW = 32'b?????????????????010?????0100111; -parameter [31:0] FSD = 32'b?????????????????011?????0100111; -parameter [31:0] FSQ = 32'b?????????????????100?????0100111; -parameter [31:0] C_ADDI4SPN = 32'b????????????????000???????????00; -parameter [31:0] C_FLD = 32'b????????????????001???????????00; -parameter [31:0] C_LW = 32'b????????????????010???????????00; -parameter [31:0] C_FLW = 32'b????????????????011???????????00; -parameter [31:0] C_FSD = 32'b????????????????101???????????00; -parameter [31:0] C_SW = 32'b????????????????110???????????00; -parameter [31:0] C_FSW = 32'b????????????????111???????????00; -parameter [31:0] C_ADDI = 32'b????????????????000???????????01; -parameter [31:0] C_JAL = 32'b????????????????001???????????01; -parameter [31:0] C_LI = 32'b????????????????010???????????01; -parameter [31:0] C_LUI = 32'b????????????????011???????????01; -parameter [31:0] C_SRLI = 32'b????????????????100?00????????01; -parameter [31:0] C_SRAI = 32'b????????????????100?01????????01; -parameter [31:0] C_ANDI = 32'b????????????????100?10????????01; -parameter [31:0] C_SUB = 32'b????????????????100011???00???01; -parameter [31:0] C_XOR = 32'b????????????????100011???01???01; -parameter [31:0] C_OR = 32'b????????????????100011???10???01; -parameter [31:0] C_AND = 32'b????????????????100011???11???01; -parameter [31:0] C_SUBW = 32'b????????????????100111???00???01; -parameter [31:0] C_ADDW = 32'b????????????????100111???01???01; -parameter [31:0] C_J = 32'b????????????????101???????????01; -parameter [31:0] C_BEQZ = 32'b????????????????110???????????01; -parameter [31:0] C_BNEZ = 32'b????????????????111???????????01; -parameter [31:0] C_SLLI = 32'b????????????????000???????????10; -parameter [31:0] C_FLDSP = 32'b????????????????001???????????10; -parameter [31:0] C_LWSP = 32'b????????????????010???????????10; -parameter [31:0] C_FLWSP = 32'b????????????????011???????????10; -parameter [31:0] C_MV = 32'b????????????????1000??????????10; -parameter [31:0] C_ADD = 32'b????????????????1001??????????10; -parameter [31:0] C_FSDSP = 32'b????????????????101???????????10; -parameter [31:0] C_SWSP = 32'b????????????????110???????????10; -parameter [31:0] C_FSWSP = 32'b????????????????111???????????10; -parameter [31:0] C_NOP = 32'b????????????????0000000000000001; -parameter [31:0] C_ADDI16SP = 32'b????????????????011?00010?????01; -parameter [31:0] C_JR = 32'b????????????????1000?????0000010; -parameter [31:0] C_JALR = 32'b????????????????1001?????0000010; -parameter [31:0] C_EBREAK = 32'b????????????????1001000000000010; -parameter [31:0] C_LD = 32'b????????????????011???????????00; -parameter [31:0] C_SD = 32'b????????????????111???????????00; -parameter [31:0] C_ADDIW = 32'b????????????????001???????????01; -parameter [31:0] C_LDSP = 32'b????????????????011???????????10; -parameter [31:0] C_SDSP = 32'b????????????????111???????????10; diff --git a/tb/tb_wt_dcache/hdl/tb.sv b/tb/tb_wt_dcache/hdl/tb.sv index 0ff089258..24277f154 100644 --- a/tb/tb_wt_dcache/hdl/tb.sv +++ b/tb/tb_wt_dcache/hdl/tb.sv @@ -41,6 +41,9 @@ module tb; parameter logic [63:0] CachedAddrEnd = 64'hFFFF_FFFF_FFFF_FFFF; localparam ariane_cfg_t ArianeDefaultConfig = '{ + RASDepth: 2, + BTBEntries: 32, + BHTEntries: 128, // idempotent region NrNonIdempotentRules: 0, NonIdempotentAddrBase: {64'b0}, diff --git a/tb/tb_wt_icache/hdl/tb.sv b/tb/tb_wt_icache/hdl/tb.sv index 0a6b62ec7..45b06c907 100644 --- a/tb/tb_wt_icache/hdl/tb.sv +++ b/tb/tb_wt_icache/hdl/tb.sv @@ -40,16 +40,19 @@ module tb; parameter logic [63:0] CachedAddrEnd = 64'hFFFF_FFFF_FFFF_FFFF; localparam ariane_cfg_t Cfg = '{ + RASDepth: 2, + BTBEntries: 32, + BHTEntries: 128, // idempotent region - NrNonIdempotentRules: 0, + NrNonIdempotentRules: 0, NonIdempotentAddrBase: {64'b0}, NonIdempotentLength: {64'b0}, // executable region - NrExecuteRegionRules: 0, + NrExecuteRegionRules: 0, ExecuteRegionAddrBase: {64'h0}, ExecuteRegionLength: {64'h0}, // cached region - NrCachedRegionRules: 1, + NrCachedRegionRules: 1, CachedRegionAddrBase: {CachedAddrBeg}, CachedRegionLength: {CachedAddrEnd-CachedAddrBeg+64'b1}, // cache config