diff --git a/src/branch_unit.sv b/src/branch_unit.sv
index f75bd1163..fe32908d8 100644
--- a/src/branch_unit.sv
+++ b/src/branch_unit.sv
@@ -92,7 +92,7 @@ module branch_unit (
         branch_result_o                  = next_pc;
 
         // save PC - we need this to get the target row in the branch target buffer
-        // we play this trick with the branch instruction which wraps a byte boundary:
+        // we play this trick with the branch instruction which wraps a word boundary:
         //  /---------- Place the prediction on this PC
         // \/
         // ____________________________________________________
diff --git a/src/load_unit.sv b/src/load_unit.sv
index 3eed47c94..43af698b7 100644
--- a/src/load_unit.sv
+++ b/src/load_unit.sv
@@ -224,6 +224,8 @@ module load_unit (
         if (ex_i.valid) begin
             // the next state will be the idle state
             NS = IDLE;
+            // pop load
+            pop_ld_o = 1'b1;
         end
 
         // if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in a extra stage
@@ -247,9 +249,9 @@ module load_unit (
                 valid_o = 1'b1;
         end
         // an exception occurred during translation
-        if (CS == WAIT_TRANSLATION && ex_i.valid) begin
+        if (ex_i.valid) begin
             valid_o = 1'b1;
-        // if we are waiting for the translation to finish do not give a valid signal
+        // if we are waiting for the translation to finish do not give a valid signal yet
         end else if (CS == WAIT_TRANSLATION) begin
             valid_o = 1'b0;
         end