diff --git a/.gitignore b/.gitignore index 5de42ffdf..045476b06 100644 --- a/.gitignore +++ b/.gitignore @@ -29,6 +29,7 @@ __pycache__ dvt_build.log xrun.history xrun.log +xrun.key xcelium.d/ waves.shm/ *.log @@ -65,3 +66,6 @@ transcript tools/spike tools/verilator* *_results/ +*.signature_output +ucli.key +vcs.cmd diff --git a/.readthedocs.yaml b/.readthedocs.yaml index cef3d888f..fd184371c 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -4,10 +4,10 @@ version: 2 -#build: -# os: "ubuntu-20.04" -# tools: -# python: "3.9" +build: + os: "ubuntu-20.04" + tools: + python: "3.9" # Build from the docs/VerifStrat/source directory with Sphinx sphinx: diff --git a/bin/ci_check b/bin/ci_check index 362e7c60c..42cf58c12 100755 --- a/bin/ci_check +++ b/bin/ci_check @@ -47,7 +47,7 @@ import subprocess import pprint import yaml import re -import distutils.spawn +import shutil if (sys.version_info < (3,0,0)): print ('Requires python 3') @@ -243,7 +243,7 @@ if (args.verilator): elif (args.simulator == None): print ('Must specify a simulator. Type `ci_check -h` to see how') exit(0) -elif (not(distutils.spawn.find_executable(args.simulator))): +elif (not(shutil.which(args.simulator))): print ('ERROR: simulator='+args.simulator+' but executable not found') exit(0) else: diff --git a/cv32e40p/bsp/Makefile b/cv32e40p/bsp/Makefile index 17ead027d..ee05577a8 100644 --- a/cv32e40p/bsp/Makefile +++ b/cv32e40p/bsp/Makefile @@ -6,7 +6,7 @@ RISCV_AR = $(RISCV_EXE_PREFIX)ar SRC = crt0.S handlers.S syscalls.c vectors.S OBJ = crt0.o handlers.o syscalls.o vectors.o LIBCV-VERIF = libcv-verif.a -CFLAGS ?= -Os -g -static -mabi=ilp32 -march=rv32imc -Wall -pedantic +CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(CV_SW_MARCH) -Wall -pedantic all: $(LIBCV-VERIF) @@ -26,7 +26,9 @@ clean: vars: @echo "make bsp variables:" @echo " CV_SW_TOOLCHAIN = $(CV_SW_TOOLCHAIN)" + @echo " CV_SW_MARCH = $(CV_SW_MARCH)" @echo " RISCV = $(RISCV)" @echo " RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)" @echo " RISCV_GCC = $(RISCV_GCC)" + @echo " RISCV_MARCH = $(RISCV_MARCH)" diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index a8d3822e9..503bf9135 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -18,7 +18,7 @@ CV_CORE_BRANCH ?= master CV_CORE_HASH ?= fcd5968 CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer, but -# ilogically equivalent RTL with respect to v1.0.0 RTL freeze version. +# logically equivalent RTL with respect to v1.0.0 RTL freeze version. # There are some implementation and testbench updates in the above hash. # Set CV_CORE_TAG as below to point to the exact cv32e40p repo as that used at RTL freeze #CV_CORE_TAG ?= cv32e40p_v1.0.0 @@ -36,6 +36,13 @@ COMPLIANCE_BRANCH ?= master # 2020-08-19 COMPLIANCE_HASH ?= c21a2e86afa3f7d4292a2dd26b759f3f29cde497 +# This Spike repo is only cloned when the DPI disassembler needs to be rebuilt. +# Typically users can simply use the checked-in shared library. +# Should you need to, the command is "make dpi_dasm". +DPI_DASM_SPIKE_REPO ?= https://github.com/riscv/riscv-isa-sim.git +DPI_DASM_SPIKE_BRANCH ?= master +DPI_DASM_SPIKE_HASH ?= 8faa928819fb551325e76b463fc0c978e22f5be3 + # SVLIB SVLIB_REPO ?= https://bitbucket.org/verilab/svlib/src/master/svlib SVLIB_BRANCH ?= master diff --git a/cv32e40p/sim/core/Makefile b/cv32e40p/sim/core/Makefile index 574b355ef..d044441ea 100644 --- a/cv32e40p/sim/core/Makefile +++ b/cv32e40p/sim/core/Makefile @@ -453,7 +453,7 @@ xrun-test: xrun-all $(TEST_PROGRAM_PATH)/$(TEST)/$(TEST).hex $(XRUN_FLAGS) \ -f $(CV_CORE_MANIFEST) \ $(TBSRC_PKG) $(TBSRC) \ - +firmware=$(TEST_PROGRAM_PATH)/$(TEST)/$(CUSTOM_PROG).hex + +firmware=$(TEST_PROGRAM_PATH)/$(TEST)/$(TEST).hex # Cadence Xcelium xrun cleanup .PHONY: xrun-clean xrun-clean-all diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p.flist b/cv32e40p/tb/uvmt/uvmt_cv32e40p.flist index d5a0052cd..c39b64f95 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p.flist +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p.flist @@ -28,7 +28,7 @@ -f ${DV_UVMA_INTERRUPT_PATH}/uvma_interrupt_pkg.flist -f ${DV_UVMA_OBI_MEMORY_PATH}/src/uvma_obi_memory_pkg.flist -f ${DV_UVMA_DEBUG_PATH}/uvma_debug_pkg.flist --f $(DV_SVLIB_PATH)/svlib_pkg.flist +-f ${DV_SVLIB_PATH}/svlib_pkg.flist // Environments -f ${DV_UVME_PATH}/uvme_cv32e40p_pkg.flist diff --git a/cv32e40p/tests/programs/custom/debug_test/debug_test.c b/cv32e40p/tests/programs/custom/debug_test/debug_test.c index 7efc789ca..b597960fa 100644 --- a/cv32e40p/tests/programs/custom/debug_test/debug_test.c +++ b/cv32e40p/tests/programs/custom/debug_test/debug_test.c @@ -20,6 +20,7 @@ ******************************************************************************* */ +#include #include #include diff --git a/lib/dpi_dasm/lib/Linux64/libdpi_dasm.so b/lib/dpi_dasm/lib/Linux64/libdpi_dasm.so index a6b363bac..9208fe3a4 100755 Binary files a/lib/dpi_dasm/lib/Linux64/libdpi_dasm.so and b/lib/dpi_dasm/lib/Linux64/libdpi_dasm.so differ diff --git a/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv b/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv index b8f8aab9a..4248927e4 100644 --- a/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv +++ b/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv @@ -373,6 +373,7 @@ covergroup cg_rtype_sc_w ( `ISACOV_CP_BITWISE(cp_rs1_toggle, instr.rs1_value, 1) `ISACOV_CP_BITWISE(cp_rs2_toggle, instr.rs2_value, 1) `ISACOV_CP_BITWISE_0_0(cp_rd_toggle, instr.rd_value, 1) + // Note: "More specific failure codes might be defined in future versions or extensions to the ISA." endgroup : cg_rtype_sc_w diff --git a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv index f994c165b..c53baa07e 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv @@ -49,23 +49,23 @@ covergroup cg_obi(string name, option.name = name; we: coverpoint (trn.access_type) { - ignore_bins IGN_WRITE = {UVMA_OBI_MEMORY_ACCESS_WRITE} with (!write_enabled); - ignore_bins IGN_READ = {UVMA_OBI_MEMORY_ACCESS_READ} with (!read_enabled); + ignore_bins IGN_WRITE = {UVMA_OBI_MEMORY_ACCESS_WRITE} with ((item >= 0) && (!write_enabled)); + ignore_bins IGN_READ = {UVMA_OBI_MEMORY_ACCESS_READ} with ((item >= 0) && (!read_enabled)); bins WRITE = {UVMA_OBI_MEMORY_ACCESS_WRITE}; bins READ = {UVMA_OBI_MEMORY_ACCESS_READ}; } memtype: coverpoint (trn.memtype) { - ignore_bins IGN_MEMTYPE = {[0:$]} with (!is_1p2); + ignore_bins IGN_MEMTYPE = {[0:$]} with ((item >= 0) && (!is_1p2)); } prot: coverpoint (trn.prot) { - ignore_bins IGN_MEMTYPE = {[0:$]} with (!is_1p2); + ignore_bins IGN_MEMTYPE = {[0:$]} with ((item >= 0) && (!is_1p2)); ignore_bins IGN_RSVD_PRIV = {3'b100, 3'b101}; } err: coverpoint (trn.err) { - ignore_bins IGN_ERR = {[0:$]} with (!is_1p2); + ignore_bins IGN_ERR = {[0:$]} with ((item >=0 ) && (!is_1p2)); } endgroup : cg_obi diff --git a/mk/Common.mk b/mk/Common.mk index 6da0852e9..14cc99b35 100644 --- a/mk/Common.mk +++ b/mk/Common.mk @@ -671,12 +671,13 @@ vcs-unit-test: vcs-run DPI_DASM_SRC = $(DPI_DASM_PKG)/dpi_dasm.cxx $(DPI_DASM_PKG)/spike/disasm.cc $(DPI_DASM_SPIKE_PKG)/disasm/regnames.cc DPI_DASM_ARCH = $(shell uname)$(shell getconf LONG_BIT) -DPI_DASM_LIB = $(DPI_DASM_PKG)/lib/$(DPI_DASM_ARCH)/libdpi_dasm.so +DPI_DASM_LIB ?= $(DPI_DASM_PKG)/lib/$(DPI_DASM_ARCH)/libdpi_dasm.so DPI_DASM_CFLAGS = -shared -fPIC -std=c++11 DPI_DASM_INC = -I$(DPI_DASM_PKG) -I$(DPI_INCLUDE) -I$(DPI_DASM_SPIKE_PKG)/riscv -I$(DPI_DASM_SPIKE_PKG)/softfloat DPI_DASM_CXX = g++ dpi_dasm: $(DPI_DASM_SPIKE_PKG) + $(CLONE_DPI_DASM_SPIKE_CMD) $(DPI_DASM_CXX) $(DPI_DASM_CFLAGS) $(DPI_DASM_INC) $(DPI_DASM_SRC) -o $(DPI_DASM_LIB) ############################################################################### diff --git a/mk/uvmt/vcs.mk b/mk/uvmt/vcs.mk index 6c86f9260..617d30389 100644 --- a/mk/uvmt/vcs.mk +++ b/mk/uvmt/vcs.mk @@ -30,12 +30,15 @@ endif # Executables VCS = $(CV_SIM_PREFIX) vcs -SIMV = $(CV_TOOL_PREFIX) simv -licwait 20 +#SIMV = $(CV_TOOL_PREFIX) simv -licwait 20 +SIMV = simv -licwait 20 DVE = $(CV_TOOL_PREFIX) dve #VERDI = $(CV_TOOL_PREFIX)verdi URG = $(CV_SIM_PREFIX) urg # Paths +VCS_RESULTS ?= vcs_results +VCS_OUT ?= $(SIM_CFG_RESULTS)/vcs_out VCS_DIR ?= $(SIM_CFG_RESULTS)/vcs.d VCS_ELAB_COV = -cm line+cond+tgl+fsm+branch+assert -cm_dir $(MAKECMDGOALS)/$(MAKECMDGOALS).vdb @@ -47,12 +50,14 @@ VCS_UVM_VERBOSITY ?= UVM_MEDIUM # Flags #VCS_UVMHOME_ARG ?= /opt/uvm/1800.2-2017-0.9/ -VCS_UVMHOME_ARG ?= /opt/synopsys/vcs-mx/O-2018.09-SP1-1/etc/uvm -VCS_UVM_ARGS ?= +incdir+$(VCS_UVMHOME_ARG)/src $(VCS_UVMHOME_ARG)/src/uvm_pkg.sv +UVM_VERBOSITY=$(VCS_UVM_VERBOSITY) -ntb_opts uvm-1.2 +#VCS_UVMHOME_ARG ?= /opt/synopsys/vcs-mx/O-2018.09-SP1-1/etc/uvm +VCS_UVMHOME_ARG ?= /synopsys/vcs/S-2021.09-SP1/etc/uvm +VCS_UVM_ARGS ?= +define+UVM +incdir+$(VCS_UVMHOME_ARG)/src $(VCS_UVMHOME_ARG)/src/uvm_pkg.sv +UVM_VERBOSITY=$(VCS_UVM_VERBOSITY) -ntb_opts uvm-1.2 VCS_COMP_FLAGS ?= -lca -sverilog \ - $(SV_CMP_FLAGS) $(VCS_UVM_ARGS) $(VCS_TIMESCALE) \ - -assert svaext -race=all -ignore unique_checks -full64 + $(SV_CMP_FLAGS) $(VCS_UVM_ARGS) $(VCS_TIMESCALE) \ + -assert svaext -race=all -ignore unique_checks -full64 + VCS_GUI ?= VCS_RUN_COV = -cm line+cond+tgl+fsm+branch+assert -cm_dir $(MAKECMDGOALS).vdb @@ -62,6 +67,13 @@ VCS_PMA_INC += +incdir+$(TBSRC_HOME)/uvmt \ +incdir+$(CV_CORE_COREVDV_PKG)/ldgen \ +incdir+$(abspath $(MAKE_PATH)/../../../lib/mem_region_gen) +# Need to re-define the LIB paths for VCS to drop the "*.so" extension. +DPI_DASM_LIB = $(DPI_DASM_PKG)/lib/$(DPI_DASM_ARCH)/libdpi_dasm +SVLIB_LIB = $(SVLIB_PKG)/../svlib_dpi + +# Required by dpi_dasm target +DPI_INCLUDE ?= $(shell dirname $(shell which vcs))/../include + ############################################################################### # Common QUIET flag defaults to -quiet unless VERBOSE is set ifeq ($(call IS_YES,$(VERBOSE)),YES) @@ -145,21 +157,17 @@ endif VCS_RUN_BASE_FLAGS ?= $(VCS_GUI) \ $(VCS_PLUSARGS) +ntb_random_seed=$(RNDSEED) \ - -sv_lib $(VCS_OVP_MODEL_DPI) \ - -sv_lib $(DPI_DASM_LIB) \ - -sv_lib $(abspath $(SVLIB_LIB)) + -sv_lib $(VCS_OVP_MODEL_DPI) \ + -sv_lib $(DPI_DASM_LIB) \ + -sv_lib $(abspath $(SVLIB_LIB)) # Simulate using latest elab -VCS_RUN_FLAGS ?= +VCS_RUN_FLAGS = -assert nopostproc VCS_RUN_FLAGS += $(VCS_RUN_BASE_FLAGS) VCS_RUN_FLAGS += $(VCS_RUN_WAVES_FLAGS) VCS_RUN_FLAGS += $(VCS_RUN_COV_FLAGS) VCS_RUN_FLAGS += $(USER_RUN_FLAGS) -# Special var to point to tool and installation dependent path of DPI headers. -# Used to recompile dpi_dasm_spike if needed (by default, not needed). -DPI_INCLUDE ?= $(shell dirname $(shell which vcs))/../lib - ############################################################################### # Targets @@ -190,11 +198,12 @@ VCS_COMP = $(VCS_COMP_FLAGS) \ $(UVM_PLUSARGS) comp: mk_vcs_dir $(CV_CORE_PKG) $(SVLIB_PKG) $(OVP_MODEL_DPI) - cd $(SIM_CFG_RESULTS)/$(CFG) && $(VCS) $(VCS_COMP) -top uvmt_$(CV_CORE_LC)_tb @echo "$(BANNER)" - @echo "* $(SIMULATOR) compile complete" + @echo "* $(SIMULATOR) compile" @echo "* Log: $(SIM_CFG_RESULTS)/vcs.log" @echo "$(BANNER)" + mkdir -p $(VCS_OUT) + cd $(VCS_OUT) && $(VCS) $(VCS_COMP) -top uvmt_$(CV_CORE_LC)_tb ifneq ($(call IS_NO,$(COMP)),NO) VCS_SIM_PREREQ = comp @@ -218,21 +227,22 @@ gen_ovpsim_ic: export IMPERAS_TOOLS=$(SIM_RUN_RESULTS)/ovpsim.ic ################################################################################ -# The new general test target - +# The general test target test: $(VCS_SIM_PREREQ) hex gen_ovpsim_ic - echo $(IMPERAS_TOOLS) - mkdir -p $(SIM_RUN_RESULTS) + @echo "$(BANNER)" + @echo "* Running simulation with $(SIMULATOR)" + @echo "$(BANNER)" + mkdir -p $(SIM_RUN_RESULTS) && \ cd $(SIM_RUN_RESULTS) && \ - $(VCS_RESULTS)/$(CFG)/$(SIMV) \ - -l vcs-$(TEST_NAME).log \ - -cm_name $(TEST_NAME) $(VCS_RUN_FLAGS) \ - $(CFG_PLUSARGS) \ - $(TEST_PLUSARGS) \ - +UVM_TESTNAME=$(TEST_UVM_TEST) \ - +elf_file=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).elf \ - +firmware=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).hex \ - +itb_file=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).itb + $(VCS_OUT)/$(SIMV) \ + -l vcs-$(TEST_NAME).log \ + -cm_name $(TEST_NAME) $(VCS_RUN_FLAGS) \ + $(CFG_PLUSARGS) \ + $(TEST_PLUSARGS) \ + +UVM_TESTNAME=$(TEST_UVM_TEST) \ + +elf_file=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).elf \ + +firmware=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).hex \ + +itb_file=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).itb ############################################################################### # Run a single test-program from the RISC-V Compliance Test-suite. The parent @@ -303,7 +313,7 @@ gen_corev-dv: $(GEN_PLUSARGS) for (( idx=${GEN_START_INDEX}; idx < $$((${GEN_START_INDEX} + ${GEN_NUM_TESTS})); idx++ )); do \ cp -f ${BSP}/link_corev-dv.ld ${SIM_TEST_RESULTS}/$$idx/test_program/link.ld; \ - cp ${VCS_COREVDV_RESULTS}/${TEST}/${TEST}_$$idx.S ${SIM_TEST_RESULTS}/$$idx/test_program; \ + cp ${SIM_COREVDV_RESULTS}/${TEST}/${TEST}_$$idx.S ${SIM_TEST_RESULTS}/$$idx/test_program; \ done ################################################################################ @@ -354,5 +364,5 @@ clean_eclipse: rm -rf workspace # All generated files plus the clone of the RTL -clean_all: clean clean_eclipse clean_riscv-dv clean_test_programs clean-bsp clean_compliance clean_embench clean_dpi_dasm_spike clean_svlib +clean_all: clean clean_eclipse clean_riscv-dv clean_test_programs clean_bsp clean_compliance clean_embench clean_dpi_dasm_spike clean_svlib rm -rf $(CV_CORE_PKG)