diff --git a/README.md b/README.md
index 691a46a04..545f067e3 100644
--- a/README.md
+++ b/README.md
@@ -213,7 +213,7 @@ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.ya
 
 # COREV-APU FPGA Emulation
 
-We currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual) and the [Agilex 7 Development Kit](https://www.intel.la/content/www/xl/es/products/details/fpga/development-kits/agilex/agf014.html).
+We currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual) and the [Agilex 7 Development Kit](https://www.intel.la/content/www/xl/es/products/details/fpga/development-kits/agilex/agf014.html). In order the run the FPGA build scripts you will need to use Xilinx 2018.2.
 
 - **Genesys 2**
     
diff --git a/ci/install-verilator.sh b/ci/install-verilator.sh
index b100a656d..d9415fcbe 100755
--- a/ci/install-verilator.sh
+++ b/ci/install-verilator.sh
@@ -10,7 +10,7 @@ fi
 VERILATOR_REPO="https://github.com/verilator/verilator.git"
 VERILATOR_BRANCH="master"
 # Use the release tag instead of a full SHA1 hash.
-VERILATOR_HASH="v5.008"
+VERILATOR_HASH="v5.028"
 VERILATOR_PATCH="$ROOT/verif/regress/verilator-v5.patch"
 
 VERILATOR_BUILD_DIR=$PWD/verilator-$VERILATOR_HASH/verilator
diff --git a/docs/scripts/classes.py b/docs/scripts/classes.py
index cfc79cb14..f11b5ec8b 100644
--- a/docs/scripts/classes.py
+++ b/docs/scripts/classes.py
@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 
 class Parameter:
diff --git a/docs/scripts/define_blacklist.py b/docs/scripts/define_blacklist.py
index bdee4b2fd..2ed886339 100644
--- a/docs/scripts/define_blacklist.py
+++ b/docs/scripts/define_blacklist.py
@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 
 def define_blacklist(parameters):
diff --git a/docs/scripts/parameters_extractor.py b/docs/scripts/parameters_extractor.py
index 09365c263..e5ef4dd76 100644
--- a/docs/scripts/parameters_extractor.py
+++ b/docs/scripts/parameters_extractor.py
@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import sys
 import os
diff --git a/docs/scripts/spec_builder.py b/docs/scripts/spec_builder.py
index 261e2d243..1abb760dd 100755
--- a/docs/scripts/spec_builder.py
+++ b/docs/scripts/spec_builder.py
@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import re
 import sys
diff --git a/verif/regress/install-verilator.sh b/verif/regress/install-verilator.sh
index a70fc145f..b1c4e5ef4 100755
--- a/verif/regress/install-verilator.sh
+++ b/verif/regress/install-verilator.sh
@@ -18,7 +18,7 @@ fi
 VERILATOR_REPO="https://github.com/verilator/verilator.git"
 VERILATOR_BRANCH="master"
 # Use the release tag instead of a full SHA1 hash.
-VERILATOR_HASH="v5.008"
+VERILATOR_HASH="v5.028"
 VERILATOR_PATCH="$ROOT_PROJECT/verif/regress/verilator-v5.patch"
 
 # Unset historical variable VERILATOR_ROOT as it collides with the build process.
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
index 4c5075ec8..9ff991f69 100644
--- a/verif/sim/cva6.py
+++ b/verif/sim/cva6.py
@@ -1004,7 +1004,7 @@ def check_spike_version():
     logging.info(f"- stderr:\n\n{user_spike_stderr_string}")
     # Run 'ldd' on Spike binary and print contents of stdout and stderr.
     spike_ldd = subprocess.run(
-        "/bin/ldd $SPIKE_PATH/spike", capture_output=True, text=True, shell=True
+        "ldd $SPIKE_PATH/spike", capture_output=True, text=True, shell=True
     )
     spike_ldd_stdout = spike_ldd.stdout.strip()
     spike_ldd_stderr = spike_ldd.stderr.strip()
@@ -1030,7 +1030,7 @@ def check_spike_version():
 
 
 def check_verilator_version():
-  REQUIRED_VERILATOR_VERSION = "5.008"
+  REQUIRED_VERILATOR_VERSION = "5.028"
 
   verilator_version_string = run_cmd("verilator --version")
   logging.info(f"Verilator Version: {verilator_version_string.strip()}")