From cb01e46f7550e6857e243c4b654fe1a530290ff7 Mon Sep 17 00:00:00 2001
From: Michael Schaffner <schaffner@iis.ee.ethz.ch>
Date: Fri, 31 Aug 2018 12:53:52 +0200
Subject: [PATCH] move cache-specific files to separate folder

---
 Makefile                                            | 13 +++++++------
 src/{ => cache_subsystem}/cache_ctrl.sv             |  0
 src/{ => cache_subsystem}/lfsr.sv                   |  0
 src/{ => cache_subsystem}/miss_handler.sv           |  0
 src/{ => cache_subsystem}/std_cache_subsystem.sv    |  6 +++---
 src/{icache.sv => cache_subsystem/std_icache.sv}    |  2 +-
 .../std_nbdcache.sv}                                |  2 +-
 src/{ => cache_subsystem}/vdregs.sv                 |  0
 8 files changed, 12 insertions(+), 11 deletions(-)
 rename src/{ => cache_subsystem}/cache_ctrl.sv (100%)
 rename src/{ => cache_subsystem}/lfsr.sv (100%)
 rename src/{ => cache_subsystem}/miss_handler.sv (100%)
 rename src/{ => cache_subsystem}/std_cache_subsystem.sv (98%)
 rename src/{icache.sv => cache_subsystem/std_icache.sv} (99%)
 rename src/{nbdcache.sv => cache_subsystem/std_nbdcache.sv} (99%)
 rename src/{ => cache_subsystem}/vdregs.sv (100%)

diff --git a/Makefile b/Makefile
index c33334e69..46a1a46ee 100755
--- a/Makefile
+++ b/Makefile
@@ -19,11 +19,11 @@ verilator      ?= verilator
 target-options ?=
 # Sources
 # Package files -> compile first
-ariane_pkg := include/riscv_pkg.sv     \
-              src/debug/dm_pkg.sv      \
-              include/ariane_pkg.sv    \
-              include/std_cache_pkg.sv \
-              include/axi_if.sv
+ariane_pkg := include/riscv_pkg.sv       \
+              src/debug/dm_pkg.sv        \
+              include/ariane_pkg.sv      \
+              include/std_cache_pkg.sv   \
+			  include/axi_if.sv
 
 # utility modules
 util := $(wildcard src/util/*.svh)         \
@@ -40,7 +40,8 @@ dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
 dpi_hdr := $(wildcard tb/dpi/*.h)
 # this list contains the standalone components
 src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))      \
-        $(wildcard bootrom/*.sv)                                       \
+        $(wildcard src/cache_subsystem/*.sv)                           \
+		$(wildcard bootrom/*.sv)                                       \
         $(wildcard src/axi_slice/*.sv)                                 \
         $(wildcard src/clint/*.sv)                                     \
         $(wildcard src/axi_node/*.sv)                                  \
diff --git a/src/cache_ctrl.sv b/src/cache_subsystem/cache_ctrl.sv
similarity index 100%
rename from src/cache_ctrl.sv
rename to src/cache_subsystem/cache_ctrl.sv
diff --git a/src/lfsr.sv b/src/cache_subsystem/lfsr.sv
similarity index 100%
rename from src/lfsr.sv
rename to src/cache_subsystem/lfsr.sv
diff --git a/src/miss_handler.sv b/src/cache_subsystem/miss_handler.sv
similarity index 100%
rename from src/miss_handler.sv
rename to src/cache_subsystem/miss_handler.sv
diff --git a/src/std_cache_subsystem.sv b/src/cache_subsystem/std_cache_subsystem.sv
similarity index 98%
rename from src/std_cache_subsystem.sv
rename to src/cache_subsystem/std_cache_subsystem.sv
index 856b1e1bd..a6739b7b4 100644
--- a/src/std_cache_subsystem.sv
+++ b/src/cache_subsystem/std_cache_subsystem.sv
@@ -45,7 +45,7 @@ module std_cache_subsystem #(
    input  logic                           dcache_flush_i,         // high until acknowledged
    output logic                           dcache_flush_ack_o,     // send a single cycle acknowledge signal when the cache is flushed
    output logic                           dcache_miss_o,          // we missed on a ld/st
-   // AMO interface
+   // AMO interface (not functional yet)
    input  logic                           dcache_amo_commit_i,    // commit atomic memory operation
    output logic                           dcache_amo_valid_o,     // we have a valid AMO result
    output logic [63:0]                    dcache_amo_result_o,    // result of atomic memory operation
@@ -61,7 +61,7 @@ module std_cache_subsystem #(
 );
 
 
-   icache #(
+   std_icache #(
    ) i_icache (
       .clk_i             ( clk_i                 ),
       .rst_ni            ( rst_ni                ),
@@ -80,7 +80,7 @@ module std_cache_subsystem #(
    // Port 0: PTW
    // Port 1: Load Unit
    // Port 2: Store Unit
-   nbdcache #(
+   std_nbdcache #(
       .CACHE_START_ADDR ( CACHE_START_ADDR )
    ) i_nbdcache (
       .clk_i              ( clk_i                  ),
diff --git a/src/icache.sv b/src/cache_subsystem/std_icache.sv
similarity index 99%
rename from src/icache.sv
rename to src/cache_subsystem/std_icache.sv
index be77c030f..81ebbf80a 100644
--- a/src/icache.sv
+++ b/src/cache_subsystem/std_icache.sv
@@ -16,7 +16,7 @@
 import ariane_pkg::*;
 import std_cache_pkg::*;
 
-module icache  #(
+module std_icache  #(
 )(
     input  logic                     clk_i,
     input  logic                     rst_ni,
diff --git a/src/nbdcache.sv b/src/cache_subsystem/std_nbdcache.sv
similarity index 99%
rename from src/nbdcache.sv
rename to src/cache_subsystem/std_nbdcache.sv
index 8d697d1e3..ce1d0730d 100644
--- a/src/nbdcache.sv
+++ b/src/cache_subsystem/std_nbdcache.sv
@@ -15,7 +15,7 @@
 import ariane_pkg::*;
 import std_cache_pkg::*;
 
-module nbdcache #(
+module std_nbdcache #(
         parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000
 )(
     input  logic                           clk_i,       // Clock
diff --git a/src/vdregs.sv b/src/cache_subsystem/vdregs.sv
similarity index 100%
rename from src/vdregs.sv
rename to src/cache_subsystem/vdregs.sv