diff --git a/ariane.sv b/ariane.sv index 266546a00..38ac4db2b 100644 --- a/ariane.sv +++ b/ariane.sv @@ -71,7 +71,7 @@ module ariane logic [31:0] instr_rdata_id_o; logic is_compressed_id_o; logic illegal_c_insn_id_o; - logic [63:0] pc_if_o; + logic [63:0] pc_if_o, imm_o; logic [63:0] pc_id_o; logic comparison_result_o; logic lsu_ready_o; @@ -151,6 +151,7 @@ module ariane .operator_o ( operator_o ), .operand_a_o ( operand_a_o ), .operand_b_o ( operand_b_o ), + .imm_o ( imm_o ), .trans_id_o ( trans_id_o ), .alu_ready_i ( alu_ready_i ), .alu_valid_o ( alu_valid_i ), @@ -176,6 +177,7 @@ module ariane .operator_i ( operator_o ), .operand_a_i ( operand_a_o ), .operand_b_i ( operand_b_o ), + .imm_i ( imm_o ), .trans_id_i ( trans_id_o ), .comparison_result_o ( comparison_result_o ), diff --git a/decoder.sv b/decoder.sv index 188f6d25e..b84a9e7eb 100644 --- a/decoder.sv +++ b/decoder.sv @@ -175,13 +175,50 @@ module decoder ( end OPCODE_STORE: begin - // TODO: Implement + instruction_o.fu = LSU; imm_select = SIMM; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; + // determine store size + unique case (instr.stype.funct3) + 3'b000: + instruction_o.op = SB; + 3'b001: + instruction_o.op = SH; + 3'b010: + instruction_o.op = SW; + 3'b011: + instruction_o.op = SD; + default: + illegal_instr_o = 1'b1; + endcase end OPCODE_LOAD: begin - // TODO: Implement + instruction_o.fu = LSU; imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; + // determine load size and signed type + unique case (instr.itype.funct3) + 3'b000: + instruction_o.op = LB; + 3'b001: + instruction_o.op = LH; + 3'b010: + instruction_o.op = LW; + 3'b100: + instruction_o.op = LBU; + 3'b101: + instruction_o.op = LHU; + 3'b110: + instruction_o.op = LW; + 3'b011: + instruction_o.op = LD; + default: + illegal_instr_o = 1'b1; + endcase + end OPCODE_BRANCH: begin diff --git a/ex_stage.sv b/ex_stage.sv index cfe2df788..b5e5f686c 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -25,6 +25,7 @@ module ex_stage ( input fu_op operator_i, input logic [63:0] operand_a_i, input logic [63:0] operand_b_i, + input logic [63:0] imm_i, input logic [TRANS_ID_BITS-1:0] trans_id_i, // ALU 1 diff --git a/id_stage.sv b/id_stage.sv index ac57b89d0..a29a783f8 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -28,6 +28,7 @@ module id_stage #( output fu_op operator_o, output logic [63:0] operand_a_o, output logic [63:0] operand_b_o, + output logic [63:0] imm_o, output logic [TRANS_ID_BITS-1:0] trans_id_o, input logic alu_ready_i, @@ -128,6 +129,7 @@ module id_stage #( .operator_o (operator_o ), .operand_a_o (operand_a_o ), .operand_b_o (operand_b_o ), + .imm_o (imm_o ), .trans_id_o (trans_id_o ), .alu_ready_i (alu_ready_i ), .alu_valid_o (alu_valid_o ), diff --git a/include/ariane_pkg.svh b/include/ariane_pkg.svh index 8234166b5..af3186842 100644 --- a/include/ariane_pkg.svh +++ b/include/ariane_pkg.svh @@ -50,7 +50,7 @@ package ariane_pkg; LTS, LTU, LES, LEU, GTS, GTU, GES, GEU, EQ, NE, // comparisons SLTS, SLTU, SLETS, SLETU, // set lower than operations MRET, SRET, URET, ECALL, WRITE, READ, SET, CLEAR, // CSR functions - LD, SD, LW, SW, LH, SH, LB, SB, LBU, SBU // LSU functions + LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU, SBU // LSU functions } fu_op; // --------------- diff --git a/issue_read_operands.sv b/issue_read_operands.sv index 290436bcd..59e1e7447 100755 --- a/issue_read_operands.sv +++ b/issue_read_operands.sv @@ -33,6 +33,7 @@ module issue_read_operands ( output fu_op operator_o, output logic [63:0] operand_a_o, output logic [63:0] operand_b_o, + output logic [63:0] imm_o, // output immediate for the LSU output logic [TRANS_ID_BITS-1:0] trans_id_o, // ALU 1 input logic alu_ready_i, // FU is ready @@ -55,7 +56,7 @@ module issue_read_operands ( logic [63:0] operand_a_regfile, operand_b_regfile; // operands coming from regfile // output flipflop (ID <-> EX) - logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q; + logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q, imm_n, imm_q; logic alu_valid_n, alu_valid_q; logic [TRANS_ID_BITS-1:0] trans_id_n, trans_id_q; fu_op operator_n, operator_q; @@ -68,6 +69,7 @@ module issue_read_operands ( assign operator_o = operator_q; assign alu_valid_o = alu_valid_q; assign trans_id_o = trans_id_q; + assign imm_o = imm_q; // --------------- // Issue Stage // --------------- @@ -160,11 +162,16 @@ module issue_read_operands ( operand_a_n = issue_instr_i.ex.epc; end - // or is it an immediate (including PC) - if (issue_instr_i.use_imm) begin + // or is it an immediate (including PC), this is not the case for a store + if (issue_instr_i.use_imm && issue_instr_i.op != SD + && issue_instr_i.op != SW + && issue_instr_i.op != SH + && issue_instr_i.op != SB + && issue_instr_i.op != SBU ) begin operand_b_n = issue_instr_i.result; end - + // immediates are the third operands in the store case + imm_n = issue_instr_i.result; trans_id_n = issue_instr_i.trans_id; operator_n = issue_instr_i.op; end diff --git a/lsu.sv b/lsu.sv index dedc4d215..1d31a536a 100644 --- a/lsu.sv +++ b/lsu.sv @@ -47,4 +47,7 @@ module lsu ( ); + // exception unit + // misaligned detector + endmodule \ No newline at end of file