diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 12f346c0e..ad4e1ec82 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -17,7 +17,8 @@ module csr_regfile import ariane_pkg::*; #( parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address parameter int AsidWidth = 1, parameter int unsigned NrCommitPorts = 2, - parameter int unsigned NrPMPEntries = 8 + parameter int unsigned NrPMPEntries = 8, + parameter int unsigned MHPMCounterNum = 6 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -85,7 +86,8 @@ module csr_regfile import ariane_pkg::*; #( output logic perf_we_o, // PMPs output riscv::pmpcfg_t [15:0] pmpcfg_o, // PMP configuration containing pmpcfg for max 16 PMPs - output logic [15:0][riscv::PLEN-3:0] pmpaddr_o // PMP addresses + output logic [15:0][riscv::PLEN-3:0] pmpaddr_o, // PMP addresses + output logic [31:0] mcountinhibit_o ); // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; @@ -141,7 +143,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d; - + logic [MHPMCounterNum+3-1:0] mcountinhibit_d,mcountinhibit_q; assign pmpcfg_o = pmpcfg_q[15:0]; assign pmpaddr_o = pmpaddr_q; @@ -242,6 +244,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MARCHID: csr_rdata = ARIANE_MARCHID; riscv::CSR_MIMPID: csr_rdata = '0; // not implemented riscv::CSR_MHARTID: csr_rdata = hart_id_i; + riscv::CSR_MCOUNTINHIBIT: csr_rdata = mcountinhibit_q; // Counters and Timers riscv::CSR_MCYCLE: csr_rdata = cycle_q[riscv::XLEN-1:0]; riscv::CSR_MCYCLEH: if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32]; else read_access_exception = 1'b1; @@ -257,14 +260,37 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MHPM_EVENT_5, riscv::CSR_MHPM_EVENT_6, riscv::CSR_MHPM_EVENT_7, - riscv::CSR_MHPM_EVENT_8: csr_rdata = perf_data_i; + riscv::CSR_MHPM_EVENT_8, + riscv::CSR_MHPM_EVENT_9, + riscv::CSR_MHPM_EVENT_10, + riscv::CSR_MHPM_EVENT_11, + riscv::CSR_MHPM_EVENT_12, + riscv::CSR_MHPM_EVENT_13, + riscv::CSR_MHPM_EVENT_14, + riscv::CSR_MHPM_EVENT_15, + riscv::CSR_MHPM_EVENT_16, + riscv::CSR_MHPM_EVENT_17, + riscv::CSR_MHPM_EVENT_18, + riscv::CSR_MHPM_EVENT_19, + riscv::CSR_MHPM_EVENT_20, + riscv::CSR_MHPM_EVENT_21, + riscv::CSR_MHPM_EVENT_22, + riscv::CSR_MHPM_EVENT_23, + riscv::CSR_MHPM_EVENT_24, + riscv::CSR_MHPM_EVENT_25, + riscv::CSR_MHPM_EVENT_26, + riscv::CSR_MHPM_EVENT_27, + riscv::CSR_MHPM_EVENT_28, + riscv::CSR_MHPM_EVENT_29, + riscv::CSR_MHPM_EVENT_30, + riscv::CSR_MHPM_EVENT_31 : csr_rdata = perf_data_i; riscv::CSR_MHPM_COUNTER_3, riscv::CSR_MHPM_COUNTER_4, riscv::CSR_MHPM_COUNTER_5, riscv::CSR_MHPM_COUNTER_6, riscv::CSR_MHPM_COUNTER_7, - riscv::CSR_MHPM_COUNTER_8, + riscv::CSR_MHPM_COUNTER_8, riscv::CSR_MHPM_COUNTER_9, riscv::CSR_MHPM_COUNTER_10, riscv::CSR_MHPM_COUNTER_11, @@ -287,7 +313,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MHPM_COUNTER_28, riscv::CSR_MHPM_COUNTER_29, riscv::CSR_MHPM_COUNTER_30, - riscv::CSR_MHPM_COUNTER_31 : csr_rdata = perf_data_i; + riscv::CSR_MHPM_COUNTER_31 : csr_rdata = perf_data_i; riscv::CSR_MHPM_COUNTER_3H, riscv::CSR_MHPM_COUNTER_4H, @@ -318,6 +344,68 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MHPM_COUNTER_29H, riscv::CSR_MHPM_COUNTER_30H, riscv::CSR_MHPM_COUNTER_31H : if (riscv::XLEN == 32) csr_rdata = perf_data_i; else read_access_exception = 1'b1; + + // Performance counters (User Mode - R/O Shadows) + riscv::CSR_HPM_COUNTER_3, + riscv::CSR_HPM_COUNTER_4, + riscv::CSR_HPM_COUNTER_5, + riscv::CSR_HPM_COUNTER_6, + riscv::CSR_HPM_COUNTER_7, + riscv::CSR_HPM_COUNTER_8, + riscv::CSR_HPM_COUNTER_9, + riscv::CSR_HPM_COUNTER_10, + riscv::CSR_HPM_COUNTER_11, + riscv::CSR_HPM_COUNTER_12, + riscv::CSR_HPM_COUNTER_13, + riscv::CSR_HPM_COUNTER_14, + riscv::CSR_HPM_COUNTER_15, + riscv::CSR_HPM_COUNTER_16, + riscv::CSR_HPM_COUNTER_17, + riscv::CSR_HPM_COUNTER_18, + riscv::CSR_HPM_COUNTER_19, + riscv::CSR_HPM_COUNTER_20, + riscv::CSR_HPM_COUNTER_21, + riscv::CSR_HPM_COUNTER_22, + riscv::CSR_HPM_COUNTER_23, + riscv::CSR_HPM_COUNTER_24, + riscv::CSR_HPM_COUNTER_25, + riscv::CSR_HPM_COUNTER_26, + riscv::CSR_HPM_COUNTER_27, + riscv::CSR_HPM_COUNTER_28, + riscv::CSR_HPM_COUNTER_29, + riscv::CSR_HPM_COUNTER_30, + riscv::CSR_HPM_COUNTER_31 : csr_rdata = perf_data_i; + + riscv::CSR_HPM_COUNTER_3H, + riscv::CSR_HPM_COUNTER_4H, + riscv::CSR_HPM_COUNTER_5H, + riscv::CSR_HPM_COUNTER_6H, + riscv::CSR_HPM_COUNTER_7H, + riscv::CSR_HPM_COUNTER_8H, + riscv::CSR_HPM_COUNTER_9H, + riscv::CSR_HPM_COUNTER_10H, + riscv::CSR_HPM_COUNTER_11H, + riscv::CSR_HPM_COUNTER_12H, + riscv::CSR_HPM_COUNTER_13H, + riscv::CSR_HPM_COUNTER_14H, + riscv::CSR_HPM_COUNTER_15H, + riscv::CSR_HPM_COUNTER_16H, + riscv::CSR_HPM_COUNTER_17H, + riscv::CSR_HPM_COUNTER_18H, + riscv::CSR_HPM_COUNTER_19H, + riscv::CSR_HPM_COUNTER_20H, + riscv::CSR_HPM_COUNTER_21H, + riscv::CSR_HPM_COUNTER_22H, + riscv::CSR_HPM_COUNTER_23H, + riscv::CSR_HPM_COUNTER_24H, + riscv::CSR_HPM_COUNTER_25H, + riscv::CSR_HPM_COUNTER_26H, + riscv::CSR_HPM_COUNTER_27H, + riscv::CSR_HPM_COUNTER_28H, + riscv::CSR_HPM_COUNTER_29H, + riscv::CSR_HPM_COUNTER_30H, + riscv::CSR_HPM_COUNTER_31H : if (riscv::XLEN == 32) csr_rdata = perf_data_i; else read_access_exception = 1'b1; + // custom (non RISC-V) cache control riscv::CSR_DCACHE: csr_rdata = dcache_q; riscv::CSR_ICACHE: csr_rdata = icache_q; @@ -370,6 +458,8 @@ module csr_regfile import ariane_pkg::*; #( satp = satp_q; instret = instret_q; + mcountinhibit_d = mcountinhibit_q; + // -------------------- // Counters // -------------------- @@ -378,11 +468,11 @@ module csr_regfile import ariane_pkg::*; #( if (!debug_mode_q) begin // increase instruction retired counter for (int i = 0; i < NrCommitPorts; i++) begin - if (commit_ack_i[i] && !ex_i.valid) instret++; + if (commit_ack_i[i] && !ex_i.valid && !mcountinhibit_q[2]) instret++; end instret_d = instret; // increment the cycle count - if (ENABLE_CYCLE_COUNT) cycle_d = cycle_q + 1'b1; + if (ENABLE_CYCLE_COUNT && !mcountinhibit_q[0]) cycle_d = cycle_q + 1'b1; else cycle_d = instret; end @@ -605,6 +695,7 @@ module csr_regfile import ariane_pkg::*; #( mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP; mip_d = (mip_q & ~mask) | (csr_wdata & mask); end + riscv::CSR_MCOUNTINHIBIT: mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]}; // performance counters riscv::CSR_MCYCLE: cycle_d[riscv::XLEN-1:0] = csr_wdata; riscv::CSR_MCYCLEH: if (riscv::XLEN == 32) cycle_d[63:32] = csr_wdata; else update_access_exception = 1'b1; @@ -616,7 +707,30 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MHPM_EVENT_5, riscv::CSR_MHPM_EVENT_6, riscv::CSR_MHPM_EVENT_7, - riscv::CSR_MHPM_EVENT_8 : begin perf_we_o = 1'b1; perf_data_o = csr_wdata;end + riscv::CSR_MHPM_EVENT_8, + riscv::CSR_MHPM_EVENT_9, + riscv::CSR_MHPM_EVENT_10, + riscv::CSR_MHPM_EVENT_11, + riscv::CSR_MHPM_EVENT_12, + riscv::CSR_MHPM_EVENT_13, + riscv::CSR_MHPM_EVENT_14, + riscv::CSR_MHPM_EVENT_15, + riscv::CSR_MHPM_EVENT_16, + riscv::CSR_MHPM_EVENT_17, + riscv::CSR_MHPM_EVENT_18, + riscv::CSR_MHPM_EVENT_19, + riscv::CSR_MHPM_EVENT_20, + riscv::CSR_MHPM_EVENT_21, + riscv::CSR_MHPM_EVENT_22, + riscv::CSR_MHPM_EVENT_23, + riscv::CSR_MHPM_EVENT_24, + riscv::CSR_MHPM_EVENT_25, + riscv::CSR_MHPM_EVENT_26, + riscv::CSR_MHPM_EVENT_27, + riscv::CSR_MHPM_EVENT_28, + riscv::CSR_MHPM_EVENT_29, + riscv::CSR_MHPM_EVENT_30, + riscv::CSR_MHPM_EVENT_31 : begin perf_we_o = 1'b1; perf_data_o = csr_wdata;end riscv::CSR_MHPM_COUNTER_3, riscv::CSR_MHPM_COUNTER_4, @@ -1160,6 +1274,7 @@ module csr_regfile import ariane_pkg::*; #( assign mprv = (debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv; assign debug_mode_o = debug_mode_q; assign single_step_o = dcsr_q.step; + assign mcountinhibit_o = {{29-MHPMCounterNum{1'b0}}, mcountinhibit_q}; // sequential process always_ff @(posedge clk_i or negedge rst_ni) begin @@ -1191,6 +1306,7 @@ module csr_regfile import ariane_pkg::*; #( mtval_q <= {riscv::XLEN{1'b0}}; dcache_q <= {{riscv::XLEN-1{1'b0}}, 1'b1}; icache_q <= {{riscv::XLEN-1{1'b0}}, 1'b1}; + mcountinhibit_q <= '0; // supervisor mode registers sepc_q <= {riscv::XLEN{1'b0}}; scause_q <= {riscv::XLEN{1'b0}}; @@ -1234,6 +1350,7 @@ module csr_regfile import ariane_pkg::*; #( mtval_q <= mtval_d; dcache_q <= dcache_d; icache_q <= icache_d; + mcountinhibit_q <= mcountinhibit_d; // supervisor mode registers sepc_q <= sepc_d; scause_q <= scause_d; diff --git a/core/cva6.sv b/core/cva6.sv index 97e15a9e6..4d3e630fe 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -193,6 +193,7 @@ module cva6 import ariane_pkg::*; #( logic single_step_csr_commit; riscv::pmpcfg_t [15:0] pmpcfg; logic [15:0][riscv::PLEN-3:0] pmpaddr; + logic [31:0] mcountinhibit_csr_perf; // ---------------------------- // Performance Counters <-> * // ---------------------------- @@ -554,7 +555,8 @@ module cva6 import ariane_pkg::*; #( .AsidWidth ( ASID_WIDTH ), .DmBaseAddress ( ArianeCfg.DmBaseAddress ), .NrCommitPorts ( NR_COMMIT_PORTS ), - .NrPMPEntries ( ArianeCfg.NrPMPEntries ) + .NrPMPEntries ( ArianeCfg.NrPMPEntries ), + .MHPMCounterNum ( MHPMCounterNum ) ) csr_regfile_i ( .flush_o ( flush_csr_ctrl ), .halt_csr_o ( halt_csr_ctrl ), @@ -601,6 +603,7 @@ module cva6 import ariane_pkg::*; #( .perf_we_o ( we_csr_perf ), .pmpcfg_o ( pmpcfg ), .pmpaddr_o ( pmpaddr ), + .mcountinhibit_o ( mcountinhibit_csr_perf ), .debug_req_i, .ipi_i, .irq_i, @@ -639,7 +642,8 @@ module cva6 import ariane_pkg::*; #( .l1_dcache_access_i ( dcache_req_ports_ex_cache ), .miss_vld_bits_i ( miss_vld_bits ), .i_tlb_flush_i ( flush_tlb_ctrl_ex ), - .stall_issue_i ( stall_issue ) + .stall_issue_i ( stall_issue ), + .mcountinhibit_i ( mcountinhibit_csr_perf ) ); end diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index eaa7b5661..9d9fae956 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -710,6 +710,7 @@ package ariane_pkg; // Performance counter // ------------------- localparam bit PERF_COUNTER_EN = cva6_config_pkg::CVA6ConfigPerfCounterEn; + localparam int unsigned MHPMCounterNum = 6; // -------------------- // Atomics diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv index ace12bccb..bb17e56d0 100644 --- a/core/include/riscv_pkg.sv +++ b/core/include/riscv_pkg.sv @@ -368,12 +368,36 @@ package riscv; CSR_MIE = 12'h304, CSR_MTVEC = 12'h305, CSR_MCOUNTEREN = 12'h306, + CSR_MCOUNTINHIBIT = 12'h320, CSR_MHPM_EVENT_3 = 12'h323, //Machine performance monitoring Event Selector CSR_MHPM_EVENT_4 = 12'h324, //Machine performance monitoring Event Selector CSR_MHPM_EVENT_5 = 12'h325, //Machine performance monitoring Event Selector CSR_MHPM_EVENT_6 = 12'h326, //Machine performance monitoring Event Selector CSR_MHPM_EVENT_7 = 12'h327, //Machine performance monitoring Event Selector CSR_MHPM_EVENT_8 = 12'h328, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_9 = 12'h329, //Reserved + CSR_MHPM_EVENT_10 = 12'h32A, //Reserved + CSR_MHPM_EVENT_11 = 12'h32B, //Reserved + CSR_MHPM_EVENT_12 = 12'h32C, //Reserved + CSR_MHPM_EVENT_13 = 12'h32D, //Reserved + CSR_MHPM_EVENT_14 = 12'h32E, //Reserved + CSR_MHPM_EVENT_15 = 12'h32F, //Reserved + CSR_MHPM_EVENT_16 = 12'h330, //Reserved + CSR_MHPM_EVENT_17 = 12'h331, //Reserved + CSR_MHPM_EVENT_18 = 12'h332, //Reserved + CSR_MHPM_EVENT_19 = 12'h333, //Reserved + CSR_MHPM_EVENT_20 = 12'h334, //Reserved + CSR_MHPM_EVENT_21 = 12'h335, //Reserved + CSR_MHPM_EVENT_22 = 12'h336, //Reserved + CSR_MHPM_EVENT_23 = 12'h337, //Reserved + CSR_MHPM_EVENT_24 = 12'h338, //Reserved + CSR_MHPM_EVENT_25 = 12'h339, //Reserved + CSR_MHPM_EVENT_26 = 12'h33A, //Reserved + CSR_MHPM_EVENT_27 = 12'h33B, //Reserved + CSR_MHPM_EVENT_28 = 12'h33C, //Reserved + CSR_MHPM_EVENT_29 = 12'h33D, //Reserved + CSR_MHPM_EVENT_30 = 12'h33E, //Reserved + CSR_MHPM_EVENT_31 = 12'h33F, //Reserved CSR_MSCRATCH = 12'h340, CSR_MEPC = 12'h341, CSR_MCAUSE = 12'h342, @@ -488,35 +512,64 @@ package riscv; CSR_INSTRET = 12'hC02, CSR_INSTRETH = 12'hC82, // Performance counters (User Mode - R/O Shadows) - CSR_L1_ICACHE_MISS = 12'hC03, // L1 Instr Cache Miss - CSR_L1_DCACHE_MISS = 12'hC04, // L1 Data Cache Miss - CSR_ITLB_MISS = 12'hC05, // ITLB Miss - CSR_DTLB_MISS = 12'hC06, // DTLB Miss - CSR_LOAD = 12'hC07, // Loads - CSR_STORE = 12'hC08, // Stores - CSR_EXCEPTION = 12'hC09, // Taken exceptions - CSR_EXCEPTION_RET = 12'hC0A, // Exception return - CSR_BRANCH_JUMP = 12'hC0B, // Software change of PC - CSR_CALL = 12'hC0C, // Procedure call - CSR_RET = 12'hC0D, // Procedure Return - CSR_MIS_PREDICT = 12'hC0E, // Branch mis-predicted - CSR_SB_FULL = 12'hC0F, // Scoreboard full - CSR_IF_EMPTY = 12'hC10, // instruction fetch queue empty - CSR_HPM_COUNTER_17 = 12'hC11, // reserved - CSR_HPM_COUNTER_18 = 12'hC12, // reserved - CSR_HPM_COUNTER_19 = 12'hC13, // reserved - CSR_HPM_COUNTER_20 = 12'hC14, // reserved - CSR_HPM_COUNTER_21 = 12'hC15, // reserved - CSR_HPM_COUNTER_22 = 12'hC16, // reserved - CSR_HPM_COUNTER_23 = 12'hC17, // reserved - CSR_HPM_COUNTER_24 = 12'hC18, // reserved - CSR_HPM_COUNTER_25 = 12'hC19, // reserved - CSR_HPM_COUNTER_26 = 12'hC1A, // reserved - CSR_HPM_COUNTER_27 = 12'hC1B, // reserved - CSR_HPM_COUNTER_28 = 12'hC1C, // reserved - CSR_HPM_COUNTER_29 = 12'hC1D, // reserved - CSR_HPM_COUNTER_30 = 12'hC1E, // reserved - CSR_HPM_COUNTER_31 = 12'hC1F // reserved + CSR_HPM_COUNTER_3 = 12'hC03, + CSR_HPM_COUNTER_4 = 12'hC04, + CSR_HPM_COUNTER_5 = 12'hC05, + CSR_HPM_COUNTER_6 = 12'hC06, + CSR_HPM_COUNTER_7 = 12'hC07, + CSR_HPM_COUNTER_8 = 12'hC08, + CSR_HPM_COUNTER_9 = 12'hC09, // reserved + CSR_HPM_COUNTER_10 = 12'hC0A, // reserved + CSR_HPM_COUNTER_11 = 12'hC0B, // reserved + CSR_HPM_COUNTER_12 = 12'hC0C, // reserved + CSR_HPM_COUNTER_13 = 12'hC0D, // reserved + CSR_HPM_COUNTER_14 = 12'hC0E, // reserved + CSR_HPM_COUNTER_15 = 12'hC0F, // reserved + CSR_HPM_COUNTER_16 = 12'hC10, // reserved + CSR_HPM_COUNTER_17 = 12'hC11, // reserved + CSR_HPM_COUNTER_18 = 12'hC12, // reserved + CSR_HPM_COUNTER_19 = 12'hC13, // reserved + CSR_HPM_COUNTER_20 = 12'hC14, // reserved + CSR_HPM_COUNTER_21 = 12'hC15, // reserved + CSR_HPM_COUNTER_22 = 12'hC16, // reserved + CSR_HPM_COUNTER_23 = 12'hC17, // reserved + CSR_HPM_COUNTER_24 = 12'hC18, // reserved + CSR_HPM_COUNTER_25 = 12'hC19, // reserved + CSR_HPM_COUNTER_26 = 12'hC1A, // reserved + CSR_HPM_COUNTER_27 = 12'hC1B, // reserved + CSR_HPM_COUNTER_28 = 12'hC1C, // reserved + CSR_HPM_COUNTER_29 = 12'hC1D, // reserved + CSR_HPM_COUNTER_30 = 12'hC1E, // reserved + CSR_HPM_COUNTER_31 = 12'hC1F, // reserved + CSR_HPM_COUNTER_3H = 12'hC83, + CSR_HPM_COUNTER_4H = 12'hC84, + CSR_HPM_COUNTER_5H = 12'hC85, + CSR_HPM_COUNTER_6H = 12'hC86, + CSR_HPM_COUNTER_7H = 12'hC87, + CSR_HPM_COUNTER_8H = 12'hC88, + CSR_HPM_COUNTER_9H = 12'hC89, // reserved + CSR_HPM_COUNTER_10H = 12'hC8A, // reserved + CSR_HPM_COUNTER_11H = 12'hC8B, // reserved + CSR_HPM_COUNTER_12H = 12'hC8C, // reserved + CSR_HPM_COUNTER_13H = 12'hC8D, // reserved + CSR_HPM_COUNTER_14H = 12'hC8E, // reserved + CSR_HPM_COUNTER_15H = 12'hC8F, // reserved + CSR_HPM_COUNTER_16H = 12'hC90, // reserved + CSR_HPM_COUNTER_17H = 12'hC91, // reserved + CSR_HPM_COUNTER_18H = 12'hC92, // reserved + CSR_HPM_COUNTER_19H = 12'hC93, // reserved + CSR_HPM_COUNTER_20H = 12'hC94, // reserved + CSR_HPM_COUNTER_21H = 12'hC95, // reserved + CSR_HPM_COUNTER_22H = 12'hC96, // reserved + CSR_HPM_COUNTER_23H = 12'hC97, // reserved + CSR_HPM_COUNTER_24H = 12'hC98, // reserved + CSR_HPM_COUNTER_25H = 12'hC99, // reserved + CSR_HPM_COUNTER_26H = 12'hC9A, // reserved + CSR_HPM_COUNTER_27H = 12'hC9B, // reserved + CSR_HPM_COUNTER_28H = 12'hC9C, // reserved + CSR_HPM_COUNTER_29H = 12'hC9D, // reserved + CSR_HPM_COUNTER_30H = 12'hC9E, // reserved + CSR_HPM_COUNTER_31H = 12'hC9F // reserved } csr_reg_t; localparam logic [63:0] SSTATUS_UIE = 'h00000001; diff --git a/core/perf_counters.sv b/core/perf_counters.sv index 0ee068fc0..c1512d212 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -47,7 +47,8 @@ module perf_counters import ariane_pkg::*; #( input dcache_req_i_t[2:0] l1_dcache_access_i, input logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0]miss_vld_bits_i, //For Cache eviction (3ports-LOAD,STORE,PTW) input logic i_tlb_flush_i, - input logic stall_issue_i //stall-read operands + input logic stall_issue_i, //stall-read operands + input logic[31:0] mcountinhibit_i ); logic [63:0] generic_counter_d[6:1]; @@ -107,7 +108,7 @@ module perf_counters import ariane_pkg::*; #( for(int unsigned i = 1; i <= 6; i++) begin if ((!debug_mode_i) && (!we_i)) begin - if (events[i] == 1)begin + if ((events[i]) == 1 && (!mcountinhibit_i[i+2]))begin generic_counter_d[i] = generic_counter_q[i] + 1'b1;end else begin generic_counter_d[i] = 'b0;end