diff --git a/Makefile b/Makefile index 0d45a3c11..3e84e6891 100644 --- a/Makefile +++ b/Makefile @@ -81,6 +81,7 @@ ariane_pkg := include/riscv_pkg.sv \ include/axi_intf.sv \ tb/ariane_soc_pkg.sv \ include/ariane_axi_pkg.sv \ + src/pmp/include/pmp_pkg.sv \ src/fpu/src/fpnew_pkg.sv \ src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg)) @@ -138,6 +139,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ $(wildcard src/axi_node/src/*.sv) \ $(wildcard src/axi_riscv_atomics/src/*.sv) \ $(wildcard src/axi_mem_if/src/*.sv) \ + $(wildcard src/pmp/src/*.sv) \ src/rv_plic/rtl/rv_plic_target.sv \ src/rv_plic/rtl/rv_plic_gateway.sv \ src/rv_plic/rtl/plic_regmap.sv \ diff --git a/src/ariane.sv b/src/ariane.sv index 5a7da6afd..e076f7dff 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -428,7 +428,10 @@ module ariane #( // DCACHE interfaces .dcache_req_ports_i ( dcache_req_ports_cache_ex ), .dcache_req_ports_o ( dcache_req_ports_ex_cache ), - .dcache_wbuffer_empty_i ( dcache_commit_wbuffer_empty ) + .dcache_wbuffer_empty_i ( dcache_commit_wbuffer_empty ), + // PMP + .pmpcfg_i ( pmpcfg ), + .pmpaddr_i ( pmpaddr ) ); // --------- diff --git a/src/ex_stage.sv b/src/ex_stage.sv index ac9690336..9b07716d9 100644 --- a/src/ex_stage.sv +++ b/src/ex_stage.sv @@ -99,7 +99,10 @@ module ex_stage #( input amo_resp_t amo_resp_i, // response from cache subsystem // Performance counters output logic itlb_miss_o, - output logic dtlb_miss_o + output logic dtlb_miss_o, + // PMPs + input riscv::pmpcfg_t [15:0] pmpcfg_i, + input logic[ArianeCfg.NrPMPEntries-1:0] pmpaddr_i ); // ------------------------- @@ -297,7 +300,9 @@ module ex_stage #( .dcache_wbuffer_empty_i, .amo_valid_commit_i, .amo_req_o, - .amo_resp_i + .amo_resp_i, + .pmpcfg_i, + .pmpaddr_i ); endmodule diff --git a/src/load_store_unit.sv b/src/load_store_unit.sv index 87228d5b1..51667b5b9 100644 --- a/src/load_store_unit.sv +++ b/src/load_store_unit.sv @@ -66,7 +66,10 @@ module load_store_unit #( input logic dcache_wbuffer_empty_i, // AMO interface output amo_req_t amo_req_o, - input amo_resp_t amo_resp_i + input amo_resp_t amo_resp_i, + // PMP + input riscv::pmpcfg_t [15:0] pmpcfg_i, + input logic[ArianeCfg.NrPMPEntries-1:0] pmpaddr_i ); // data is misaligned logic data_misaligned; diff --git a/src/mmu.sv b/src/mmu.sv index 810c0bdc0..8ef53ca58 100644 --- a/src/mmu.sv +++ b/src/mmu.sv @@ -17,48 +17,48 @@ import ariane_pkg::*; module mmu #( - parameter int unsigned INSTR_TLB_ENTRIES = 4, - parameter int unsigned DATA_TLB_ENTRIES = 4, - parameter int unsigned ASID_WIDTH = 1, - parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig + parameter int unsigned INSTR_TLB_ENTRIES = 4, + parameter int unsigned DATA_TLB_ENTRIES = 4, + parameter int unsigned ASID_WIDTH = 1, + parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ) ( - input logic clk_i, - input logic rst_ni, - input logic flush_i, - input logic enable_translation_i, - input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores - // IF interface - input icache_areq_o_t icache_areq_i, - output icache_areq_i_t icache_areq_o, - // LSU interface - // this is a more minimalistic interface because the actual addressing logic is handled - // in the LSU as we distinguish load and stores, what we do here is simple address translation - input exception_t misaligned_ex_i, - input logic lsu_req_i, // request address translation - input logic [riscv::VLEN-1:0] lsu_vaddr_i, // virtual address in - input logic lsu_is_store_i, // the translation is requested by a store - // if we need to walk the page table we can't grant in the same cycle - // Cycle 0 - output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB - // Cycle 1 - output logic lsu_valid_o, // translation is valid - output logic [riscv::PLEN-1:0] lsu_paddr_o, // translated address - output exception_t lsu_exception_o, // address translation threw an exception - // General control signals - input riscv::priv_lvl_t priv_lvl_i, - input riscv::priv_lvl_t ld_st_priv_lvl_i, - input logic sum_i, - input logic mxr_i, - // input logic flag_mprv_i, - input logic [43:0] satp_ppn_i, - input logic [ASID_WIDTH-1:0] asid_i, - input logic flush_tlb_i, - // Performance counters - output logic itlb_miss_o, - output logic dtlb_miss_o, - // PTW memory interface - input dcache_req_o_t req_port_i, - output dcache_req_i_t req_port_o + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic enable_translation_i, + input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores + // IF interface + input icache_areq_o_t icache_areq_i, + output icache_areq_i_t icache_areq_o, + // LSU interface + // this is a more minimalistic interface because the actual addressing logic is handled + // in the LSU as we distinguish load and stores, what we do here is simple address translation + input exception_t misaligned_ex_i, + input logic lsu_req_i, // request address translation + input logic [63:0] lsu_vaddr_i, // virtual address in + input logic lsu_is_store_i, // the translation is requested by a store + // if we need to walk the page table we can't grant in the same cycle + // Cycle 0 + output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB + // Cycle 1 + output logic lsu_valid_o, // translation is valid + output logic [63:0] lsu_paddr_o, // translated address + output exception_t lsu_exception_o, // address translation threw an exception + // General control signals + input riscv::priv_lvl_t priv_lvl_i, + input riscv::priv_lvl_t ld_st_priv_lvl_i, + input logic sum_i, + input logic mxr_i, + // input logic flag_mprv_i, + input logic [43:0] satp_ppn_i, + input logic [ASID_WIDTH-1:0] asid_i, + input logic flush_tlb_i, + // Performance counters + output logic itlb_miss_o, + output logic dtlb_miss_o, + // PTW memory interface + input dcache_req_o_t req_port_i, + output dcache_req_i_t req_port_o ); logic iaccess_err; // insufficient privilege to access this instruction page @@ -151,11 +151,11 @@ module mmu #( .dtlb_hit_i ( dtlb_lu_hit ), .dtlb_vaddr_i ( lsu_vaddr_i ), - .req_port_i ( req_port_i ), - .req_port_o ( req_port_o ), + .req_port_i ( req_port_i ), + .req_port_o ( req_port_o ), .* - ); + ); // ila_1 i_ila_1 ( // .clk(clk_i), // input wire clk diff --git a/src/pmp b/src/pmp new file mode 120000 index 000000000..2ae9b9f69 --- /dev/null +++ b/src/pmp @@ -0,0 +1 @@ +/home/mo/Documents/mixedcriticality/code/iopmp \ No newline at end of file