From d35fc6be44bf1f45415075e4573668004e936824 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=B4me?= <124148386+cathales@users.noreply.github.com>
Date: Thu, 20 Mar 2025 15:28:08 +0100
Subject: [PATCH] Apply verible suggestion

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
---
 core/cva6_rvfi.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv
index 7fd05a0d2..430dac738 100644
--- a/core/cva6_rvfi.sv
+++ b/core/cva6_rvfi.sv
@@ -341,7 +341,7 @@ module cva6_rvfi
 
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags)
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm)
-  `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_q.frm, csr.fcsr_q.fflags})
+  `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, {csr.fcsr_q.frm, csr.fcsr_q.fflags})
 
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec)
   `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr)