diff --git a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst
index 25fb716f5..45b9c5524 100644
--- a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst
+++ b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst
@@ -1,6 +1,6 @@
 ..
    Copyright (c) 2023 OpenHW Group
-   Copyright (c) 2023 Thales DIS design services SAS
+   Copyright (c) 2023 Thales
 
    SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
@@ -26,11 +26,19 @@ CV-X-IF interface specification
 Need to step1 verification. TSS/Guillaume will do.
 Refer to the CV-X-IF specification, mention the 3 supported protocol interfaces, identify the CVA6 specific features.
 
+How to use CVA6 without CV-X-IF interface
+-----------------------------------------
+This is the default configuration.
+
 How to use CV-X-IF with CVA6
 ----------------------------
 We don’t commit yet to write this section. We expect the audience to be power users.
-Use CVA6 without CV-X-IF interface
-Use CVA6 with CV-X-IF interface
-How to design a coprocessor for the CV-X-IF interface
-How to program a CV-X-IF coprocessor
 
+Use CVA6 with CV-X-IF interface
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+How to design a coprocessor for the CV-X-IF interface
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+How to program a CV-X-IF coprocessor
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/01_cva6_user/Interfaces.rst b/docs/01_cva6_user/Interfaces.rst
new file mode 100644
index 000000000..096c181f7
--- /dev/null
+++ b/docs/01_cva6_user/Interfaces.rst
@@ -0,0 +1,49 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2023 Thales
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+
+.. _cva6_interfaces:
+
+Interfaces
+==========
+
+AXI Interface
+-------------
+Need for step1 verification. Already written by MU Electronics.
+Focus on the features used by the CVA6 and refer to ARM documentation for the AXI specification (e.g. do not draw the standard chronogram).
+Features:
+* See requirement specification
+* Atomic transactions
+* “USER” bus width extension
+* Transaction ordering
+
+Debug Interface
+---------------
+Desired for step1 verification, but we can likely reuse an E4 DVplan.
+Remember: the debug module (DTM) is not in the scope, so we focus on the debug interrupt.
+How to use the interface (HW/SW). We can refer to RISC-V specifications.
+If the section is too heavy, promote it to a separate chapter.
+
+Interrupt Interface
+-------------------
+Desired for step1 verification, but we can likely reuse an E4 DVplan.
+How to use the interface (HW/SW). We can refer to RISC-V specifications.
+If the section is too heavy, promote it to a separate chapter.
+
+TRI Interface
+-------------
+Refer to OpenPiton documents.
diff --git a/docs/01_cva6_user/Parameters_Configuration.rst b/docs/01_cva6_user/Parameters_Configuration.rst
index e40fa6c07..4138b2a5f 100644
--- a/docs/01_cva6_user/Parameters_Configuration.rst
+++ b/docs/01_cva6_user/Parameters_Configuration.rst
@@ -32,36 +32,3 @@ Configurations
 A configuration is a fixed set of parameters.
 We list the parameters of the configuration for which verification activities have started.
 Give step 1 configuration (Jean-Roch?)
-
-Interfaces
-----------
-List of interface signals
-As in the RTL files.
-
-AXI Interface
-~~~~~~~~~~~~~
-Need for step1 verification. Already written by MU Electronics.
-Focus on the features used by the CVA6 and refer to ARM documentation for the AXI specification (e.g. do not draw the standard chronogram).
-Features:
-* See requirement specification
-* Atomic transactions
-* “USER” bus width extension
-* Transaction ordering
-
-Debug Interface
-~~~~~~~~~~~~~~~
-Desired for step1 verification, but we can likely reuse an E4 DVplan.
-Remember: the debug module (DTM) is not in the scope, so we focus on the debug interrupt.
-How to use the interface (HW/SW). We can refer to RISC-V specifications.
-If the section is too heavy, promote it to a separate chapter.
-
-Interrupt Interface
-~~~~~~~~~~~~~~~~~~~
-Desired for step1 verification, but we can likely reuse an E4 DVplan.
-How to use the interface (HW/SW). We can refer to RISC-V specifications.
-If the section is too heavy, promote it to a separate chapter.
-
-TRI Interface
-~~~~~~~~~~~~~
-Refer to OpenPiton documents.
-
diff --git a/docs/01_cva6_user/index.rst b/docs/01_cva6_user/index.rst
index 74bd03f6c..4d07267ed 100644
--- a/docs/01_cva6_user/index.rst
+++ b/docs/01_cva6_user/index.rst
@@ -38,5 +38,6 @@ Editor: **Jerome Quevremont**
    CSR_Cache_Control
    CSR_Performance_Counters
    Parameters_Configuration
+   Interfaces
    Core_Integration
    CVX_Interface_Coprocessor